1.3 Register Organization

1. Introduction to CPU Registers

A computer system's memory hierarchy contains several levels of storage, varying in capacity, cost, and speed. At the absolute top of this hierarchy sit CPU registers. Registers are small, temporary storage cells located directly on the processor die. They hold the data operands currently being processed, the instruction currently being executed, and the status flags representing the outcome of recent calculations.

Because registers are the closest storage to the execution units (the ALU and Control Unit), they operate at the processor's core clock rate. Without registers, the CPU would be forced to fetch operands from main memory for every single operation, creating a severe bottleneck due to memory access latency.

2. Why Registers Are Fast

To understand why registers operate orders of magnitude faster than other storage devices, we must examine their physical construction and location:

1. On-Chip Integration: Registers are fabricated directly inside the CPU core. There are no system buses to cross or off-chip wires to traverse, eliminating transmission and interconnect delays.
2. SRAM-like Active Circuitry: Unlike DRAM (which uses capacitors that must be periodically refreshed), registers are built using static flip-flop circuits. These circuits hold their binary state indefinitely as long as power is supplied, allowing instantaneous reads and writes.
3. Zero Memory Latency: Standard main memory accesses require complex row and column decoding, which takes tens of nanoseconds. Registers bypass this address translation and bus handshake phase entirely.
4. Direct Multiplexer Control: Registers are wired directly to the inputs and outputs of the ALU using high-speed multiplexers. The Control Unit can select, read from, and write to a register within a single clock phase.
5. Resource Limits: A register file typically contains only 8 to 32 entries (rarely exceeding 128). Because the address decoder logic for a small register file is tiny, it switches at maximum frequencies. Larger memories require wider decoders, which introduces capacitive load and slows down switching speeds.

3. Register Classification

The registers inside a CPU are divided into two main categories based on whether they are accessible to the programmer:

• User-Visible (Programmer-Visible) Registers: These registers can be referenced directly in assembly language instructions. They allow the programmer or compiler to minimize main memory accesses by storing temporary variables locally.
• Control and Status Registers: These registers are used by the Control Unit to direct the operation of the processor and by the operating system to monitor and control system execution state. Most of these registers are invisible to the user-level application programmer.

CPU Registers
├── User-Visible Registers
│   ├── General-Purpose (e.g., EAX, R8)
│   ├── Data Registers (e.g., DR, AC, MQ)
│   ├── Address Registers (e.g., Stack Pointer, Index, Segment)
│   └── Condition Codes (Flags visible to branches)
│
└── Control and Status Registers
    ├── Program Counter (PC)
    ├── Instruction Register (IR)
    ├── Instruction Buffer Register (IBR)
    ├── Memory Address Register (MAR)
    ├── Memory Buffer Register (MBR)
    └── Program Status Word (PSW / System Flags)
                                

4. User-Visible Registers

User-visible registers are defined by the Instruction Set Architecture (ISA). They form the register file that assembly instructions can read from or write to. They are classified into:

4.1 General-Purpose Registers (GPRs)

GPRs can hold operands for any arithmetic, logical, or address calculation instruction. Modern RISC processors utilize a flat set of symmetric GPRs (typically numbered R0 through R31) to simplify compiler register allocation. For example, in RISC-V, any GPR can be used for any integer operation (with the exception of R0, which is hardwired to zero).

4.2 Dedicated Data and Address Registers

Some architectures dedicate specific registers to either data or addresses:

• Data Registers: Used strictly to hold operand values (e.g., multipliers, addends). They cannot be used to compute memory addresses.
• Address Registers: Used to hold memory addresses for displacement, indexing, or pointer operations. Examples include:
  • Segment Pointers: In segmented architectures (like the 8086), these point to the base of code, data, stack, or extra memory blocks.
  • Index Registers: Used for indexed addressing modes, where an offset is added to a base address (e.g., SI and DI in x86).
  • Stack Pointer (SP): Points to the top of the active execution stack in memory. It is automatically incremented or decremented by push, pop, call, and return operations.

5. Control and Status Registers

Control and status registers are the internal mechanisms the Control Unit uses to orchestrate instruction execution. The most critical control registers are:

• Program Counter (PC): Contains the memory address of the next instruction to be fetched and executed. In some architectures, it is automatically updated to point to the next sequential instruction after a fetch cycle, unless a branch modifies it.
• Instruction Register (IR): Holds the binary machine code of the instruction currently being decoded and executed. The output of the IR feeds directly into the instruction decoder logic.
• Memory Address Register (MAR): Connects directly to the address bus lines. It holds the physical address in main memory that the CPU wants to read from or write to.
• Memory Buffer Register (MBR): Connects directly to the data bus lines. Also called the Memory Data Register (MDR), it holds the data read from memory or the data to be written to memory.
• Instruction Buffer Register (IBR): A specialized register found in machines that pack multiple instructions into a single memory word (such as the IAS machine). It holds the second instruction fetched from a memory word while the first is being executed, saving an extra memory read cycle.

6. How Registers Work Together During Instruction Execution

Registers do not operate in isolation. During every instruction cycle, data and addresses flow through the internal CPU registers in a coordinated sequence managed by the Control Unit.

The typical register flow for a basic memory-read instruction (e.g., loading a value from memory into a register) proceeds as follows:

  [PC] ──► [MAR] ──► (Address Bus) ──► [Main Memory]
                                             │
  [IR] ◄── [MBR] ◄── (Data Bus) ◄────────────┘
    │
    ▼
[Decoder] ──► [ALU] ──► [Destination Register] ──► [PSW Update]
                                

Let's trace each step in the sequence:

1. Address Setup: The Program Counter (PC) identifies the address of the next instruction. This address is copied to the Memory Address Register (MAR).
2. Fetch: The MAR places the address onto the address bus. Main memory retrieves the data word at that address and places it onto the data bus. The CPU reads the data bus and copies the value into the Memory Buffer Register (MBR).
3. Instruction Loading: The instruction byte(s) are transferred from the MBR to the Instruction Register (IR). The PC is incremented to point to the next instruction address.
4. Decode: The instruction decoder reads the opcode inside the IR, identifying the operation (e.g., load, store, add) and operand locations.
5. Operand Load: If the instruction requires memory data, the operand address is placed in the MAR. Memory is read, and the operand value is fetched into the MBR.
6. Execution: The ALU performs the operation using the operands from the MBR and/or general-purpose registers. The result is written to the destination register.
7. Status Update: The ALU asserts status lines to update the Program Status Word (PSW) flags based on the calculation result (e.g., zero flag, sign flag, carry flag).

7. The Program Status Word (PSW)

The Program Status Word (PSW) is a control and status register composed of individual flag flip-flops. Each flag bit represents a specific condition of the processor state or the result of the most recent ALU operation.

7.1 Standard PSW Flags

Most CPU architectures define the following core status flags within the PSW:

• Sign Flag (S): Set to 1 if the MSB of the result is 1 (indicating a negative number in 2's complement representation); set to 0 otherwise.
• Zero Flag (Z): Set to 1 if the output of the ALU is exactly zero; set to 0 otherwise. This flag is heavily used for conditional loop branches.
• Carry Flag (CY): Set to 1 if an arithmetic addition generates a carry out of the MSB, or if a subtraction generates a borrow. Used for multi-word math.
• Parity Flag (P): Set to 1 if the lower 8 bits of the result contain an even number of 1s (even parity); set to 0 for odd parity.
• Overflow Flag (V / OV): Set to 1 if an arithmetic operation on signed numbers overflows the range (e.g., adding two positive numbers yields a negative result).
• Interrupt Enable Flag (I): A control bit. Set to 1 to allow the CPU to service external maskable hardware interrupts; set to 0 to disable them.

7.2 Case Study: Intel 8085 PSW Flag Byte Layout

The historical 8-bit Intel 8085 microprocessor groups the accumulator register (A) and the flag register (F) together to form a 16-bit Program Status Word. The flag byte layout uses 5 active bits:

Table 1.3.1: Intel 8085 Flag byte layout. 'X' denotes unused bits.

8. The IAS Machine Register Datapath

To see register organization in a historical, clean context, we examine the Princeton **IAS machine** (developed by John von Neumann in the late 1940s). The IAS computer was an accumulator-based architecture. It contained 8 primary registers, each with a specific functional role:

8.1 IAS Register Inventory

• Accumulator (AC) & Multiplier Quotient (MQ): Temporary data registers used by the ALU. For a 40-bit multiplication, the most-significant 40 bits of the 80-bit product are stored in AC, and the least-significant 40 bits are stored in MQ.
• Memory Buffer Register (MBR): Holds a 40-bit word read from memory or ready to be written to memory.
• Memory Address Register (MAR): Holds the 12-bit memory address referencing one of the 1000 memory locations (addresses 0 to 999).
• Program Counter (PC): Holds the 12-bit address of the next instruction word to be fetched.
• Instruction Register (IR): Holds the 8-bit opcode of the instruction currently being executed.
• Instruction Buffer Register (IBR): Holds the right-hand instruction of a 40-bit memory word.

8.2 Dual-Instruction Word Execution (LHI vs. RHI)

The IAS machine utilized 40-bit memory words. However, each instruction was only 20 bits long (8-bit opcode + 12-bit address). Thus, every memory word contained **two instructions**:

• Left-Hand Instruction (LHI): Bits 0 to 19.
• Right-Hand Instruction (RHI): Bits 20 to 39.

To avoid fetching the same 40-bit word twice from memory, the IAS machine utilized the Instruction Buffer Register (IBR). During a fetch cycle:

1. The 40-bit word is read into the MBR.
2. The Left-Hand Instruction (LHI) opcode goes to the IR; the LHI address goes to the MAR.
3. The Right-Hand Instruction (RHI) is stored in the IBR.
4. The LHI is executed.
5. For the next instruction cycle, the CPU does not perform a memory read. Instead, it copies the RHI opcode from the IBR to the IR, and the RHI address to the MAR, and executes it.

8.3 Historical Register Evolution

Register files have evolved significantly from the early Princeton design to modern processors:

Equation 1.3.1: Historical progression of CPU register architectures.

9. Worked Examples & Numerical Problems

    Accumulator:  0011 1111  (0x3F = 63)
    Operand:      0100 0101  (0x45 = 69)
    ────────────────────────
    Result:       1000 0100  (0x84 = 132)
                                

10. Core Comparison Tables

Table 1.3.2: User-Visible vs. Control/Status Registers

Table 1.3.3: IAS Machine Register Matrix

11. Common Mistakes Students Make

12. Assessment Bank

12.1 Register Classification Exercise

  PC, RAX, MAR, SP, IR, PSW, MBR, R15

12.2 Multiple Choice Questions

12.3 Short Answer Questions

1. State two reasons why CPU registers are faster than static RAM (SRAM) cache modules.
2. Explain the function of the Auxiliary Carry (AC) flag in binary-coded decimal (BCD) arithmetic.
3. What is the difference between a general-purpose register and a dedicated data register?

12.4 Long Answer / Exam Questions

1. Trace the complete step-by-step register transfers (RTL) for fetching and executing a Left-Hand Instruction (LHI) followed by a Right-Hand Instruction (RHI) in the Princeton IAS machine. Your response must identify the role of the IBR, MBR, MAR, IR, and PC registers.
2. Discuss the physical and architectural factors that limit the size of a CPU register file. Why do modern architectures limit the registers to 32 or 16 rather than having thousands of registers?

12.5 Viva Voce Questions

1. "What is the difference between the Overflow flag and the Carry flag? Can they both be set by the same addition operation?" Model Answer: Yes, both can be set. The Carry flag represents unsigned overflow (carry out of MSB), while the Overflow flag represents signed overflow (sign bit corruption in 2's complement). For example, adding two negative numbers can generate a carry out of the MSB (CY=1) but yield a correct negative result (OV=0).
2. "What is the Program Status Word (PSW) called in ARM architecture, and how does it differ from the x86 flags register?" Model Answer: In ARM, it is called the CPSR (Current Program Status Register). It contains flag bits (N, Z, C, V) matching the standard PSW, plus control bits for processor modes and interrupt masks, but it is organized differently than x86's 32-bit EFLAGS register.