1.4 Interconnection & Bus Structures

1. Introduction to Interconnection Structures

A computer system's performance is not only determined by the speed of its CPU or the size of its memory, but also by the capacity of its interconnection pathways. The CPU must constantly fetch instructions and data operands from memory, and write results back. The I/O modules must transfer data to and from memory and issue interrupt requests to the CPU. The collection of paths connecting these modules is called the interconnection structure.

2. Why Buses Became Necessary

The evolution of computer interconnection architectures traces a path from simple, rigid connections to modern, high-speed packet-switched interfaces:

• Point-to-Point Wiring: Early computers utilized dedicated, direct wiring paths between every pair of modules that needed to communicate. While point-to-point links offer maximum throughput, their physical wiring complexity scales quadratically ($O(N^2)$). For $N$ modules, connecting every module requires $N(N-1)/2$ separate physical links, creating an unmanageable mesh of wires as systems grow.
• Bus-Based Architecture: To solve the point-to-point wiring crisis, designers introduced the shared system bus. A system bus is a shared communication pathway consisting of multiple physical wires. Only one pair of devices can communicate over the bus at any given moment. This shared topology reduces wiring complexity to $O(N)$ and allows easy expansion by plugging new modules into physical bus slots. However, the shared bus becomes a throughput bottleneck as multiple masters compete for access.
• Modern Switched Interconnects: In modern high-performance systems, shared buses have been replaced by point-to-point switched interconnects (such as PCI Express, QPI/UPI, or HyperTransport). These networks use packet-switched routing and dedicated links to allow multiple parallel transfers, bypassing the shared bus bottleneck.

3. System Bus Partitions

A typical system bus consists of 50 to hundreds of separate physical lines. These lines are grouped into three functional partitions:

• Data Bus: Transmits data bytes between modules. The number of physical lines determines the data bus width (e.g., 32 or 64 lines), which dictates how many bits the CPU can transfer in a single cycle.
• Address Bus: Transmits the source or destination address of the data on the data bus. The address bus width determines the maximum addressable memory capacity of the processor. For example, a processor with a 32-bit address bus can access $2^{32}$ bytes ($4\text{ GB}$) of physical memory space.
• Control Bus: Transmits command, timing, and status signals to coordinate bus access and operations. Key control lines include Memory Read/Write, I/O Read/Write, Transfer Acknowledge, Bus Request, Bus Grant, Clock, and Interrupt lines.

  ┌───────────┐         ┌──────────────┐         ┌─────────────┐
  │    CPU    │         │ Main Memory  │         │ I/O Module  │
  └─────┬─────┘         └──────┬───────┘         └──────┬──────┘
        │                      │                        │
  ======╪======================╪========================╪====== Data Bus
        │                      │                        │
  ======╪======================╪========================╪====== Address Bus
        │                      │                        │
  ======╪======================╪========================╪====== Control Bus
                                

4. Bus Arbitration

Because the system bus is shared, a conflict arises if multiple master devices (e.g., CPU, DMA controller) attempt to control the bus simultaneously. Bus arbitration is the process of selecting a single master to control the bus for the next cycle. Arbitration schemes are classified as:

4.1 Daisy Chain Arbitration (Serial Priority)

In a Daisy Chain scheme, all masters are connected in a serial link. When a bus request occurs:

1. A master asserts the shared Bus Request (BR) line.
2. The Arbiter responds by asserting the Bus Grant (BG) signal, which is wired to the physically closest master (Master 1).
3. If Master 1 does not need the bus, it passes the BG signal to Master 2. If a master needs the bus, it intercepts the BG signal and asserts Bus Busy (BB).

Trade-offs: Very simple and requires few control lines. However, priority is fixed by physical placement (causing starvation of distant masters), and a failure in any device's pass-through logic breaks the chain.

4.2 Polling and Independent Request Arbitration

• Polling: The arbiter contains a counter. On a request, it cycles through device addresses on a set of polling lines. The first requesting device that matches the polled address takes control. Priority can be dynamically changed by altering the starting address of the poll.
• Independent Request: Every master has its own dedicated Bus Request (BR_i) and Bus Grant (BG_i) lines to the arbiter. The arbiter resolves conflicts instantly using priority encoders. This scheme offers the fastest response time and dynamic priority masking but requires a large number of physical pins.

5. Bus Timing Models

Bus timing dictates how data transfers are coordinated over time. The two fundamental timing models are:

• Synchronous Timing: All bus events are referenced to a global, square-wave clock signal. A transfer cycle occurs within a fixed number of clock periods.
  • Pros: Simple control logic, very high speeds over short physical distances.
  • Cons: All devices must operate at the speed of the slowest device. Subject to **clock skew** (propagation delays mismatching the clock edges at distant parts of the bus).
• Asynchronous Timing: Bus events are coordinated using handshake signals. One event triggers the next, allowing devices of widely varying speeds to communicate.
  • Pros: Flexible, no clock distribution issues, no clock skew, easily interfaces slow peripherals.
  • Cons: More complex interface logic, susceptible to noise on handshaking lines.

6. Asynchronous Handshake Protocols

Asynchronous buses use handshake lines (typically Master Sync [MSYN] and Slave Sync [SSYN], or Request and Acknowledge) to coordinate transfers. Let's trace a **4-Phase Full Handshake Read Cycle**:

  Address:  === VALID =========================
               ┌────────────────┐
  Request:  ───┘                └──────────────
                     ┌────────────────┐
  Acknowledge: ──────┘                └────────
                     === DATA VALID ===
  Data Bus: ─────────▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒────────
               (1)   (2)        (3)   (4)
                                

The 4 phases of the read handshake proceed as follows:

1. Phase 1 (Master Initiates): The master places the address on the address bus. After a short delay (to allow the signals to stabilize), the master asserts the **Request** (or MSYN) line. This alerts the slave devices to decode the address.
2. Phase 2 (Slave Responds): The target slave decodes the address, fetches the requested data from its storage cells, places the data on the data bus, and asserts the **Acknowledge** (or SSYN) line.
3. Phase 3 (Master Clears Request): The master reads the data from the data bus. Once the data is successfully copied into the CPU's internal buffer (MBR), the master deasserts its **Request** line.
4. Phase 4 (Slave Clears Acknowledge): Seeing the request line go low, the slave releases the data bus and deasserts its **Acknowledge** line. The cycle is complete, and the bus is ready for the next transfer.

7. Worked Examples & Numerical Problems

8. Core Comparison Tables

Table 1.4.3: Synchronous vs. Asynchronous Timing

Table 1.4.4: Bus Arbitration Topologies

9. Common Mistakes Students Make

10. Assessment Bank

10.1 Multiple Choice Questions

10.2 Short Answer Questions

1. Why does point-to-point wiring become unmanageable as the number of CPU modules increases? State the complexity class.
2. Explain the concept of "Wait States" in a synchronous bus system.
3. State one advantage and one disadvantage of Daisy Chain bus arbitration.

10.3 Long Answer / Exam Questions

1. Illustrate the complete timing transitions of a 4-phase asynchronous write cycle. Draw the signal waveforms for Address, Request, Acknowledge, and Data lines, and detail the hardware transitions that happen in each phase.
2. Compare Daisy Chain, Polling, and Independent Request bus arbitration models. Analyze their wiring overhead (number of pins), priority flexibility, and fault-tolerance (reliability).

10.4 Viva Voce Questions

1. "What is a split-transaction bus, and how does it improve system bandwidth?" Model Answer: A split-transaction bus splits a single read operation into two separate bus cycles: a request cycle (where the master requests data) and a response cycle (where the slave returns the data). While the slave is fetching data internally, the bus is released so other devices can use it, improving overall throughput.
2. "How does a system bus differentiate between memory locations and I/O devices on a shared address bus?" Model Answer: The bus uses control lines (e.g. Memory Read/Write vs. I/O Read/Write) or memory-mapped I/O spaces (allocating a specific range of addresses to I/O devices rather than physical RAM).