1.5 Fixed/Floating Arithmetic & Representations

1. Fixed-Point Representation

In fixed-point representation, the binary point is assumed to be at a fixed location (typically at the extreme right for integers). Computer hardware uses three standard systems to represent signed integers inside a word of width $N$ bits:

• Sign-Magnitude: The most significant bit (MSB, bit $N-1$) represents the sign ($0$ for positive, $1$ for negative). The remaining $N-1$ bits hold the absolute value.
  • Range: $-(2^{N-1}-1)$ to $+(2^{N-1}-1)$.
  • Drawback: It has two representations for zero ($+0 = 00000000$ and $-0 = 10000000$), complicating ALU comparison circuits.
• 1's Complement: Positive numbers are identical to sign-magnitude. A negative number is formed by toggling every bit of its positive equivalent (bitwise NOT).
  • Range: $-(2^{N-1}-1)$ to $+(2^{N-1}-1)$.
  • Drawback: Still contains a dual representation for zero ($+0 = 00000000$ and $-0 = 11111111$).
• 2's Complement: The standard integer representation in modern CPUs. Positive numbers are unchanged. A negative number is formed by taking the 1's complement of its positive equivalent and adding $1$.
  • Range: $-2^{N-1}$ to $+(2^{N-1}-1)$.
  • Advantage: Only a single representation of zero ($00000000$). Addition and subtraction are executed using identical hardware.

1.1 Two's Complement Arithmetic and Overflow Detection

To subtract two numbers in 2's complement ($A - B$), the ALU negates the subtrahend $B$ (forming its 2's complement $-B$) and adds it to $A$: $$A - B = A + (-B)$$ During addition, an **overflow** occurs if the result of adding two $N$-bit numbers exceeds the range of the representation.

Hardware Overflow Rule: An overflow occurs if and only if the carry-in ($C_{in}$) into the sign bit (MSB) does not equal the carry-out ($C_{out}$) of the sign bit: $$\text{Overflow} = C_{in} \oplus C_{out}$$ Alternatively, adding two positive numbers that yields a negative result, or adding two negative numbers that yields a positive result, indicates overflow.

2. Floating-Point Representation (IEEE 754)

To represent very large integers or small fractions, computers use scientific notation adapted for binary. The IEEE 754 standard defines how floating-point numbers are stored:

Where:

• $S$ is the Sign Bit (1 bit, 0 = positive, 1 = negative).
• $F$ is the Fractional Significand (Mantissa), stored with an implicit, unstored **hidden bit** of value 1 preceding the binary point ($1.F$).
• $E$ is the biased Exponent. An offset (**Bias**) is added to the actual exponent to ensure the exponent field is always stored as an unsigned positive integer.

2.1 Format Layout Specifications

• Single-Precision (32-bit): 1-bit sign, 8-bit exponent (Bias = $127$), 23-bit mantissa. Stored exponent range: $1 \le E \le 254$ (actual exponents: $-126$ to $+127$).
• Double-Precision (64-bit): 1-bit sign, 11-bit exponent (Bias = $1023$), 52-bit mantissa. Stored exponent range: $1 \le E \le 2046$ (actual exponents: $-1022$ to $+1023$).

  ┌───┬───────────────┬───────────────────────────────────────────┐
  │ S │  Exponent (E) │               Fraction (F)                │
  └───┴───────────────┴───────────────────────────────────────────┘
  Bit: 31    30 - 23                   22 - 0
     (1 bit)  (8 bits)                (23 bits)
                                

2.2 Special Values Matrix

• Zero: $E = 0, F = 0$ (both $+0$ and $-0$ exist depending on $S$).
• Denormalized (Subnormal) Numbers: $E = 0, F \ne 0$. Used to represent numbers close to zero; the hidden bit becomes $0$ ($0.F$).
• Infinity ($\pm\infty$): $E = 255$ (single) or $E = 2047$ (double), $F = 0$.
• NaN (Not a Number): $E = 255$ (single) or $E = 2047$ (double), $F \ne 0$. Used to signal invalid operations (e.g., $0/0$ or $\sqrt{-1}$).

3. Integer Arithmetic: Booth's Multiplication Algorithm

Booth's algorithm is a hardware multiplication technique that treats signed 2's complement integers directly. It speeds up multiplication by replacing consecutive additions with subtraction at the start of a run of 1s and addition at the end of the run.

Let $M$ be the Multiplicand, $Q$ the Multiplier, and $A$ a running register initialized to zero. An extra single-bit flip-flop $Q_{-1}$ is placed to the right of the LSB of $Q$ and initialized to $0$. In each of the $N$ steps:

1. Examine the two bits $Q_0$ (LSB of $Q$) and $Q_{-1}$:
   • **$00$ or $11$**: Do nothing.
   • **$10$**: Subtract multiplicand $M$ from register $A$ ($A \leftarrow A - M$).
   • **$01$**: Add multiplicand $M$ to register $A$ ($A \leftarrow A + M$).
2. Perform an **Arithmetic Right Shift (ARS)** of the combined registers $[A, Q, Q_{-1}]$ by 1 bit. ARS preserves the sign of $A$ (the MSB of $A$ is shifted into itself).
3. Repeat $N$ times (where $N$ is the word size in bits). The final product is held in the concatenated registers $[A, Q]$.

4. Floating-Point Arithmetic Operations

Floating-point addition and subtraction require aligning exponents before the mantissas can be combined:

1. Exponent Comparison: Extract the exponents $E_1$ and $E_2$. Calculate the difference $d = |E_1 - E_2|$.
2. Significand Alignment: Shift the significand of the number with the smaller exponent to the right by $d$ bits. Set the exponent of the result to the larger exponent.
3. Significand Addition/Subtraction: Add or subtract the aligned significands based on the signs of the operands.
4. Normalization: Shift the resulting significand left or right so it starts with a leading $1$ (e.g. $1.F$), and increment or decrement the exponent accordingly.
5. Rounding: Round the significand to fit the target precision (using Guard, Round, and Sticky bits). If rounding causes an overflow in the significand, shift right again and increment the exponent.

5. Comprehensive Solved Examples

6. Core Comparison Tables

Table 1.5.3: Fixed-Point Ranges (for 8-bit registers)

7. Common Mistakes Students Make

8. Assessment Bank

8.1 Multiple Choice Questions

8.2 Short Answer Questions

1. Define the role of the "Hidden Bit" in IEEE 754 and explain why it is not physically stored.
2. Write the range of 16-bit signed integers in 2's complement and sign-magnitude.
3. Explain why arithmetic right shift (ARS) is used instead of logical right shift (LSR) during Booth's algorithm.

8.3 Long Answer / Exam Questions

1. Trace the Booth's multiplication algorithm step-by-step for $M = -9$ (Multiplicand) and $Q = -6$ (Multiplier) using 5-bit signed numbers. Show the trace table including A, Q, and $Q_{-1}$ at each step, and verify the final result.
2. Show the complete steps of floating-point addition to calculate the sum of $A = 0.75_{10}$ and $B = 4.25_{10}$ in IEEE 754 single-precision format. Show exponent comparison, mantissa shift alignment, addition, and normalization.

8.4 Viva Voce Questions

1. "What is a subnormal number in IEEE 754, and why do modern CPUs experience performance penalties when processing them?" Model Answer: A subnormal (denormalized) number is a floating-point value where the exponent field is all 0s but the mantissa is non-zero. They represent numbers extremely close to zero and use an implicit hidden bit of $0$. Many CPUs cannot process denormalized values in their fast hardware pipelines, forcing them to trap to microcode or software routines, causing a massive performance penalty.
2. "Why does 2's complement subtraction not require separate subtraction logic circuits in the ALU?" Model Answer: Because $A - B$ is mathematically equivalent to $A + (-B)$. The ALU can negate the input $B$ using bitwise NOT gates and setting the carry-in ($C_0$) of the adder to $1$, allowing the standard binary adder circuit to perform the subtraction.