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3.1 Memory Decoding

A processor connects to memory using three primary buses: the Address Bus, the Data Bus, and the Control Bus. However, because main memory is composed of multiple physical chips of varying sizes, the CPU must use decoding logic to select the correct chip for any given address. This chapter explores individual RAM and ROM pin interfaces, address line partitioning, and memory address map design.

Learning Objectives

  • Identify the pins and components of RAM ($CS$, $MEMR$, $MEMW$) and ROM ($CS$, $OE$) chips.
  • Explain how address lines are divided into selection lines and register displacement offsets.
  • Construct a complete RAM/ROM memory address map for a specified memory capacity and bus size.
  • Contrast high-order address decoding with fully decoded and partially decoded memory systems.
  • Justify the design efficiency of combining distinct memory chips into a unified memory map.
Prerequisites

Before studying this chapter, you should review Chapter 2.2: Accumulator Design to understand registers, control gating, and bus interfaces.

1. Memory Hierarchy and Main Memory

Within computer systems, memory is organized hierarchically to resolve the speed mismatch between the fast execution core of the CPU and slower secondary storage. At the top of the hierarchy are registers and cache, while the primary working storage is the **Main Memory**, which consists of Random Access Memory (RAM) and Read-Only Memory (ROM) chips.

2. Chip Interfaces and Control Pins

To interface with system buses, memory chips feature standard pins.

  • **RAM (Random Access Memory)**: Features bidirectional Data lines, Address inputs, and control lines.
    • **Chip Select ($CS_1, \bar{C}S_2$)**: Enable inputs. The chip is active only when $CS_1 = 1$ and $\bar{C}S_2 = 0$.
    • **Memory Read ($MEMR$)**: Asserts reading operations.
    • **Memory Write ($MEMW$)**: Asserts writing operations.
  • **ROM (Read-Only Memory)**: Features unidirectional Data output lines and Address inputs.
    • **Chip Select ($CS$)**: Enables the ROM chip outputs.
    • **Output Enable ($OE$)**: Directs ROM output to the Data Bus during a read instruction. ROM chips lack write pins because their contents are non-volatile and permanently configured.

3. Address Bus Partitioning & Selection

The physical lines of the **Address Bus** are partitioned into two sets:

  1. **Offset Lines**: The low-order bits mapped directly to the chip's internal register address inputs to select a specific byte. For a chip of size $2^K$ words, $K$ lines are allocated.
  2. **Chip Selection Lines**: The high-order bits routed to decoders or logical gates to enable a specific chip's Chip Select ($CS$) inputs. This prevents multiple chips from asserting data on the shared **Data Bus** simultaneously.
[Figure 3.1.1: Address Bus Partitioning & Decoder Schematic] 
  Address Bus (10 Bits: A9-A0)
  ├── A9, A8 ─────────────► [ 2x4 Decoder ] ──► CS lines to RAM/ROM Chips
  └── A7-A0 (8 bits) ─────► Direct to chip inputs (A7-A0 offset pins)
Figure 3.1.1: Schematic mapping how high-order address bits route to decoders to select a chip, while low-order bits address internal bytes.

4. Derivation of RAM/ROM Address Map

A **Memory Address Map** is a design table documenting which address lines are mapped to offsets and which lines are mapped to chip selection bits.

Let's design a system using:

  • One $512 \times 8$ ROM chip (requires $\log_2(512) = 9$ offset lines).
  • Four $128 \times 8$ RAM chips (requires $\log_2(128) = 7$ offset lines).
  • A 10-bit Address Bus ($A_9$ to $A_0$).

We allocate the address ranges so that RAM chips reside in lower memory, and the ROM chip resides in higher memory.

Component Hex Range A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
RAM 1 `000`–`07F` 0 0 0 x x x x x x x
RAM 2 `080`–`0FF` 0 0 1 x x x x x x x
RAM 3 `100`–`17F` 0 1 0 x x x x x x x
RAM 4 `180`–`1FF` 0 1 1 x x x x x x x
ROM `200`–`3FF` 1 x x x x x x x x x

5. Worked Examples & Traces

Execution Trace

Worked Example 3.1.1: Address Decoded Chip Activation

**Problem**: Trace how the Address Bus bits activate RAM 3 when the CPU issues a read to memory address `0x125` ($293_{10}$).

**Step-by-Step Trace**:

  1. **Convert Hex Address to Binary**: $$\text{Hex } 125 = \text{Binary } 01\ 0010\ 0101_2$$
  2. **Map Bits to Lines**: $$A_9=0, A_8=1, A_7=0, A_6=0, A_5=1, A_4=0, A_3=0, A_2=1, A_1=0, A_0=1$$
  3. **Check ROM Chip Select**: The ROM requires $A_9 = 1$. Since $A_9 = 0$, the ROM is **disabled**.
  4. **Evaluate RAM Decoder Inputs**: The four RAMs are decoded by the state of $A_9, A_8, A_7$. Here: $$A_9 A_8 A_7 = 010_2$$ This activates the decoder line matching RAM 3 ($CS_1 = 1$, $\bar{C}S_2 = 0$). RAM 1, 2, and 4 outputs remain high-impedance (disabled).
  5. **Extract Byte Offset**: The low-order bits $A_6$ to $A_0$ are: $$0100101_2 = 37_{10}$$ RAM 3 reads the byte at internal register address $37$.
Numerical Example

Worked Example 3.1.2: Memory Capacity Math

**Problem**: How many $128 \times 8$ RAM chips are required to construct a $2\text{ KB}$ memory block?

**Solution**:

  1. Convert $2\text{ KB}$ to bytes: $$2 \times 1024 = 2048\text{ Bytes}$$
  2. Divide by single chip size (128 bytes): $$\text{Chips} = \frac{2048}{128} = 16\text{ RAM Chips}$$
Viva Voce Q&A

Oral Exam Preparation

**Question**: "What is the difference between partial decoding and full decoding in memory interface design?"

**Answer**: In **full decoding**, every address line on the bus is connected either to selection decoder inputs or offset lines, giving each byte a single address. In **partial decoding**, some high-order address lines are left unconnected, creating duplicate address ranges (aliases) that map to the same physical memory, which simplifies gate wiring at the cost of wasting address space.

Common Mistakes to Avoid

Revision Summary & Takeaways

  • Memory chips interface with system Address, Data, and Control buses.
  • RAM chips use $MEMR$, $MEMW$, and bidirectional Data buffers, whereas ROM chips use $OE$ and lack write control lines.
  • Address maps partition lines into chip select decoders and byte registers.
How this chapter connects to the next

We have seen how standard RAM decodes memory locations by their numerical addresses. In Chapter 3.2: Associative Memory, we scale this interface to build content-addressable memory, where data is searched and retrieved by value using comparison match gates rather than numerical addresses.

Check Your Understanding

1. How many address lines are required to select a specific byte within a 4 KB ROM chip?
Short Answer Question: Why does a ROM chip lack a Write ($MEMW$) control pin?
View Model Answer ROM contains non-volatile, read-only firmware program blocks. Since the CPU cannot alter the stored values of ROM dynamically during execution, no write control line ($MEMW$) is routed to the chip interface, only an Output Enable ($OE$) control line for reads.

References

  1. **ref-notes-syed-arsalaan**: Handwritten Lecture Notes, Page 73 (Memory Decoders). [Local Verified]
  2. **ref-notes-class**: Class COA Lecture Notes, Page 32 (RAM Address Configurations). [Local Verified]
  3. **ref-book-mano**: M. Morris Mano, *Computer System Architecture*, 3rd Edition, Chapter 12. [Pending Verification]
  4. **ref-lecture-sengupta-26**: Prof. Indranil Sengupta, NPTEL COA, Lecture 26 (Main Memory Decoders). [Pending Verification]