3.10 Direct Memory Access

Interrupt-driven transfers involve CPU instruction cycles for every byte transferred, which saturates performance during high-speed transfers. Direct Memory Access (DMA) bypasses the CPU, using a dedicated controller to manage block transfers directly with RAM. This chapter explores DMA bus handshakes, internal registers, and Cycle Stealing vs. Burst Mode transfers.

Learning Objectives

Define DMA terminology: Bus Request ($BR$), Bus Grant ($BG$), Cycle Stealing, Burst Transfer, Tri-state, and Word Count.
Explain how the CPU releases the system address, data, and control buses into a high-impedance (tri-state) mode upon granting the bus.
Compute total execution times and clock overheads for a block of data transferred via Cycle Stealing vs. Burst Mode.
Contrast the roles of CPU and DMA Controller during initial parameter setup vs. actual data transfer phases.
Evaluate the impact of DMA activity on normal CPU instruction execution speeds during dense memory-bound programs.

Prerequisites

Before studying this chapter, you should review Chapter 3.8: Modes of Transfer to understand programmed vs. interrupt-initiated I/O execution.

1. The Principle of Direct Memory Access

During standard I/O, every word must pass through CPU registers. **Direct Memory Access (DMA)** resolves this CPU bottleneck by delegating bus mastership to a dedicated **DMA Controller**. When active, the DMA Controller writes data blocks directly from the peripheral interface to RAM.

2. Bus Arbitration Handshake Timing

To take control of the buses, the DMA controller and CPU execute a hardware handshake: - **Bus Request ($BR$)**: The DMA controller asserts this line to request bus release. - **Bus Grant ($BG$)**: The CPU detects $BR$, completes its current bus cycle, places its Address, Data, and Control lines in **Tri-State (high-impedance)** mode, and asserts $BG$ (high).

3. DMA Controller Hardware Registers

A typical DMA controller contains three key registers: - **Address Register**: Holds the physical RAM address of the target block. Increments after each byte transferred. - **Word Count Register**: Holds the number of bytes to transfer. Decrements after each byte. - **Control Register**: Configures read/write directions ($MEMR$, $MEMW$, $IOR$, $IOW$).

4. Operational Transfer Modes

DMA controllers operate in one of two modes: - **Burst Mode (Block Transfer)**: The DMA controller retains bus mastership until the entire block of data is transferred. The CPU is halted during this period. - **Cycle Stealing Mode**: The DMA controller requests the bus, transfers a single byte, and releases the bus. This "steals" one clock cycle from the CPU, minimizing CPU stalls.

5. Worked Examples & Traces

Execution Trace

Worked Example 3.10.1: DMA Bus Ownership Trace

**Problem**: Trace the sequence of bus signals and register states during a single-byte DMA write to RAM.

**Step-by-Step Execution Trace**:

**Initialization**: The CPU writes the target RAM address (`0x2000`) and word count ($1$) to the DMA controller registers, then enters normal execution.
**Request Phase**: The peripheral asserts the DMA request line ($REQ$). The DMA Controller asserts **Bus Request ($BR = 1$)** on the system Control Bus.
**Release Phase**: The CPU completes its current bus cycle, places its Address and Data buses in tri-state (high-impedance), and asserts **Bus Grant ($BG = 1$)**.
**Transfer Phase**: The DMA Controller takes control of the **Address Bus** and **Control Bus**: - Places address `0x2000` on the Address Bus. - Asserts I/O read (**$IOR = 0$**) and memory write (**$MEMW = 0$**) simultaneously. - The peripheral places the byte on the Data Bus, writing it directly to RAM location `0x2000`.
**Update Phase**: The DMA Controller increments the Address Register to `0x2001`, decrements the Word Count Register to $0$, and deasserts **$BR = 0$**.
**Restoration Phase**: The CPU detects $BR = 0$, deasserts **$BG = 0$**, restores its tri-state pins to active output mode, and resumes normal bus execution.

Viva Voce Q&A

Oral Exam Preparation

**Question**: "What does high-impedance (tri-state) mean in DMA bus arbitration?"

**Answer**: Tri-state (high-impedance) is an electrical state where the CPU's bus driver pins act as open circuits (disconnected). This prevents electrical conflicts (bus contention) when the DMA controller drives the Address, Data, and Control buses.

Common Mistakes to Avoid

Warning: Common Student Pitfalls

**Assuming CPU is inactive during setup**: Forgetting that the CPU acts as the master during initialization to write parameters (RAM address, word count) to the DMA controller.
**Confusing Cycle Stealing with Polling**: Thinking cycle stealing wastes CPU instruction cycles (explain that cycle stealing only steals raw bus access cycles, not execution cycles).

Revision Summary & Takeaways

DMA bypasses the CPU to perform direct memory-to-device block transfers.
Bus arbitration uses Bus Request ($BR$) and Bus Grant ($BG$) handshakes.
During DMA, the CPU places its buses in high-impedance (tri-state) mode.
Cycle Stealing steals one clock cycle at a time; Burst Mode halts the CPU during block transfers.

How this chapter connects to the next

We have seen how a DMA controller acts as a dedicated hardwired controller. In Chapter 3.11: Input-Output Processor, we scale this interface to explore the Input-Output Processor (IOP), which executes its own software program loops directly from memory.

Check Your Understanding

1. Which signal is asserted by the DMA controller to request control of system buses?

References

**ref-notes-syed-arsalaan**: Handwritten Lecture Notes, Page 105 (DMA Tristate Controls). [Local Verified]
**ref-notes-class**: Class COA Lecture Notes, Page 52 (Cycle Stealing). [Local Verified]
**ref-book-hamacher**: Carl Hamacher, *Computer Organization*, Chapter 4. [Pending Verification]
**ref-lecture-zilles-9**: Prof. Craig Zilles, Illinois ECE 290, Lecture 9 (Direct Memory Access). [Pending Verification]