3.4 Cache Writing Policies

When the CPU executes write instructions, it modifies data stored in the cache. To maintain data consistency, the system must synchronize these changes with main memory. This chapter explores Write-Through and Write-Back policies, the hardware implementation of the Dirty (Modify) Bit, and write-allocation miss rules.

Learning Objectives

Define cache write parameters: Write-Through, Write-Back, Write-Allocate, No-Write-Allocate, and Dirty (Modify) Bit.
Explain how the dirty bit flags cache lines that contain modified data not yet synchronized with main memory.
Compute the number of bus writes needed to execute a series of memory write operations under write-through and write-back rules.
Contrast Write-Allocate and No-Write-Allocate policies in terms of cache miss cycles and bus latency.
Evaluate the reliability risk of Write-Back cache schemes against the speed bottleneck of Write-Through schemes.

Prerequisites

Before studying this chapter, you should review Chapter 3.3: Cache Mapping (Direct) to understand cache lines and hits.

1. The Cache Write Problem

While reading data from a cache does not alter system state, writing data does. If the CPU updates a cache line, the corresponding block in main memory becomes stale. To maintain coherence, cache controllers implement write synchronization protocols on write hits.

2. Write-Through Policy

Under a **Write-Through** policy, every write operation automatically updates both the cache line and main memory simultaneously using the control bus line $MEMW$.

**Strength**: Simplicity; main memory always contains up-to-date data.
**Weakness**: Every write cycle forces a slow main memory write, stalling the CPU. To reduce stall time, systems employ a **Write Buffer** that queues write requests, allowing the CPU to resume instructions immediately.

3. Write-Back Policy

Under a **Write-Back** policy, the CPU updates only the cache line. Main memory is updated only when the cache line is evicted (replaced) by another block.

To implement this, each cache line tag is extended with a hardware flag called the **Dirty (Modify) Bit**: - **Dirty Bit = 0**: The cache block is identical to main memory. - **Dirty Bit = 1**: The cache block has been modified, and main memory is stale.

When a block is replaced: - If the dirty bit is 0, the block is overwritten immediately. - If the dirty bit is 1, the cache controller writes the block back to main memory first, then loads the new block.

4. Write Miss Policies

If the CPU writes to a block not currently in the cache (a write miss), two options exist:

**Write-Allocate (Fetch on Write)**: The missing block is loaded into cache, and the write is executed on the cache line. Typically paired with Write-Back.
**No-Write-Allocate (Write Around)**: The write is sent directly to main memory without loading the block into cache. Typically paired with Write-Through.

5. Worked Examples & Traces

Execution Trace

Worked Example 3.4.1: Write-Back Eviction Trace

**Problem**: Trace the states of the cache, dirty bits, and memory write counts for a direct-mapped cache line index `0x05` during a sequence of three operations: 1. Write to Block A (maps to index `0x05`). 2. Write to Block A. 3. Read Block B (also maps to index `0x05`).

**Step-by-Step Trace**:

**Write to Block A (Cache Hit/Miss)**: - Block A is loaded into cache index `0x05` (if not present). - Cache line data is updated. - **Dirty Bit is set to 1**. - Main memory write count $= 0$ (no write sent to memory bus).
**Write to Block A (Cache Hit)**: - Tag matches (Block A already at index `0x05`). - Cache line data is updated. - **Dirty Bit remains 1**. - Main memory write count $= 0$.
**Read Block B (Cache Miss & Conflict Eviction)**: - Index `0x05` is queried, but tag mismatches (holds Block A, requested Block B). - The controller detects that the **Dirty Bit $= 1$**. - **Eviction Phase**: The controller writes Block A from cache index `0x05` back to main memory using the control bus line $MEMW$. Memory write count increments to $1$. - **Fetch Phase**: Block B is loaded from main memory to cache index `0x05` using control line $MEMR$. - **Reset Phase**: The dirty bit is reset to $0$.

Viva Voce Q&A

Oral Exam Preparation

**Question**: "Why does a Write-Through cache configuration not require a dirty bit?"

**Answer**: In a Write-Through configuration, every write update is sent to both the cache and main memory simultaneously. Because main memory is always synchronized with the cache, there is never a mismatch, and no hardware dirty bit is needed to track modifications.

Common Mistakes to Avoid

Warning: Common Student Pitfalls

**Forgetting Write-Back Eviction cost**: Assuming that write-back caches are always faster than write-through, forgetting that eviction of a dirty block requires two sequential memory accesses (write-back old block, read-in new block).
**Assuming write-allocate is only for writes**: Forgetting that a write-allocate miss causes a standard block read from main memory.

Revision Summary & Takeaways

Write-Through updates memory immediately, while Write-Back defers updates until eviction.
Write-Back relies on a hardware Dirty Bit flag (1 = modified).
Write misses are managed via Write-Allocate or No-Write-Allocate policies.

How this chapter connects to the next

We have analyzed how caches manage physical SRAM block writes. In Chapter 3.5: Virtual Memory & Paging, we scale this hierarchy upwards to explore Virtual Memory, moving from SRAM cache lines to larger DRAM disk page frame mappings.

Check Your Understanding

1. Which parameter dictates if a cache line has been updated by the CPU but not yet written to memory?

References

**ref-notes-syed-arsalaan**: Handwritten Lecture Notes, Page 90 (Write Buffers). [Local Verified]
**ref-notes-class**: Class COA Lecture Notes, Page 39 (Write Policies). [Local Verified]
**ref-book-stallings**: William Stallings, *Computer Organization and Architecture*, Chapter 4. [Pending Verification]
**ref-lecture-sanchez-12**: Prof. Daniel Sanchez, MIT 6.004, Lecture 12 (Memory Models). [Pending Verification]