1.6 Instruction Cycle & Interrupts

1. Introduction to Instruction Processing

At its most fundamental level, CPU execution consists of a continuous cycle of fetching and executing instructions. This continuous loop is called the instruction cycle. The time required to process a single instruction is divided into major subcycles, which are further divided into clock periods or **T-states** (Timing States).

2. The Instruction Cycle Subcycles

An instruction cycle is divided into four main sequential subcycles:

1. Fetch Subcycle: The CPU reads an instruction from memory.
2. Decode Subcycle: The Control Unit decodes the opcode in the Instruction Register (IR) to identify the operation and locate any operands.
3. Execute Subcycle: The CPU performs the designated operation (e.g., ALU operations, memory read/write, branching).
4. Interrupt Subcycle: If interrupts are enabled and pending, the CPU saves its current state and branches to the service routine.

2.1 Timing States (T-States) in the Fetch Cycle

To trace the exact timing transitions of the Fetch subcycle, let's examine the Register Transfer Language (RTL) actions during the first three clock periods (T-states):

• State $T_1$ (Address Placement): The contents of the Program Counter (PC) are transferred to the Memory Address Register (MAR) via the internal bus: $$T_1:\text{MAR} \leftarrow \text{PC}$$
• State $T_2$ (Memory Read & PC Increment): The Control Unit asserts the memory read command line. The memory subsystem decodes the address in MAR and places the fetched instruction word onto the data bus. Simultaneously, the CPU increments the PC to point to the next instruction: $$T_2:\text{MBR} \leftarrow \text{Memory}, \quad \text{PC} \leftarrow \text{PC} + 1$$
• State $T_3$ (Instruction Loading): The fetched instruction byte/word is moved from the Memory Buffer Register (MBR) into the Instruction Register (IR) for decoding: $$T_3:\text{IR} \leftarrow \text{MBR}$$

  ┌───────────────────────────────── Fetch Subcycle ─────────────────────────────────┐
  │  State T1: PC ──► MAR                                                            │
  │  State T2: Memory ──► MBR, PC ──► PC + 1                                         │
  │  State T3: MBR ──► IR                                                            │
  └───────────────────────────────────────┬──────────────────────────────────────────┘
                                          ▼
                               ┌──────────────────────┐
                               │   Decode Opcode      │
                               └──────────┬───────────┘
                                          ▼
                               ┌──────────────────────┐
                               │   Execute Cycle      │
                               └──────────┬───────────┘
                                          ▼
                               ┌──────────────────────┐
                               │   Interrupt Check    │
                               └──────────┬───────────┘
                                          │  Interrupt Pending?
                                          ├─────────────────────────┐ Yes
                                          │ No                      ▼
                                          ▼                 ┌───────────────┐
                                  [Next Instruction]        │  Interrupt    │
                                  (Repeat T1-T3 Fetch)      │  Subcycle     │
                                                            └───────────────┘
                                

3. CPU Interrupt Classifications

An interrupt is an electrical signal or software instruction that temporarily suspends normal program execution, forcing the CPU to branch to a specialized routine. Interrupts are classified as:

• Hardware vs. Software:
  • Hardware Interrupt: Issued by external physical I/O modules (e.g. keyboard stroke, disk write completion) using dedicated processor pins.
  • Software Interrupt: Programmed trap instructions (e.g., `INT 21h` in x86) used to request Operating System services.
• Maskable vs. Non-Maskable (NMI):
  • Maskable: Can be disabled (masked) by clearing the Interrupt Enable (IE) flag bit inside the status register (PSW). The CPU ignores these requests while executing time-critical code blocks.
  • Non-Maskable (NMI): Cannot be disabled by software. Reserved for high-priority catastrophic hardware faults (e.g., power failure, parity memory error).
• Vectored vs. Non-Vectored (Polled):
  • Vectored: The requesting device provides a vector address index. The CPU reads this vector to locate the service routine directly in the Interrupt Vector Table (IVT).
  • Non-Vectored: All devices share a single interrupt pin. The CPU branches to a generic routine that poles (queries) every device sequentially to find the source.

4. The Interrupt Service Routine (ISR) Sequence

When the CPU detects an active, unmasked interrupt request at the end of an instruction cycle, it enters the **Interrupt Subcycle**. The CPU executes the following hardware actions:

1. State Saving (Hardware Phase): The CPU must save its current context so it can resume the program later. It decrements the Stack Pointer (SP) and pushes the Program Counter (PC) and Program Status Word (PSW) onto the stack: $$T_{int1}: \text{SP} \leftarrow \text{SP} - 1, \quad \text{Memory}[\text{SP}] \leftarrow \text{PC}_{high}$$ $$T_{int2}: \text{SP} \leftarrow \text{SP} - 1, \quad \text{Memory}[\text{SP}] \leftarrow \text{PC}_{low}$$ $$T_{int3}: \text{SP} \leftarrow \text{SP} - 1, \quad \text{Memory}[\text{SP}] \leftarrow \text{PSW}$$
2. Interrupt Acknowledge & Vector Lookup: The CPU asserts the Interrupt Acknowledge (INTA) control line. It reads the interrupt vector index from the data bus, references the Interrupt Vector Table (IVT) in memory, and loads the target ISR start address into the PC: $$\text{PC} \leftarrow \text{IVT}[\text{Vector}]$$
3. ISR Execution (Software Phase): The CPU begins executing the ISR instructions at the address loaded in PC. The first instructions in the ISR typically save any general-purpose registers (GPRs) onto the stack (using `PUSH`).
4. Return from Interrupt (RETI): The final instruction of the ISR is always a Return from Interrupt (`RETI`) instruction. When executed: - The CPU restores any saved GPRs (using `POP`). - The CPU pops the PSW and PC off the stack: $$\text{PSW} \leftarrow \text{Memory}[\text{SP}], \quad \text{SP} \leftarrow \text{SP} + 1$$ $$\text{PC} \leftarrow \text{Memory}[\text{SP}], \quad \text{SP} \leftarrow \text{SP} + 2$$ - The CPU resumes the interrupted program at the restored PC address.

5. Comprehensive Solved Examples

6. Core Comparison Tables

Table 1.6.3: Vectored vs. Polled (Non-Vectored) Interrupts

7. Common Mistakes Students Make

8. Assessment Bank

8.1 Multiple Choice Questions

8.2 Short Answer Questions

1. Trace the Register Transfer Language (RTL) operations that occur during the Fetch subcycle timing states ($T_1, T_2, T_3$).
2. Contrast Vectored Interrupts and Polled Interrupts. Which has lower latency?
3. Why must the CPU save the Program Status Word (PSW) on the stack during an interrupt?

8.3 Long Answer / Exam Questions

1. Detail the complete hardware and software sequence that occurs when an external hardware interrupt is asserted. Trace the register modifications, stack pointer adjustments, and memory accesses step-by-step from request to RETI.
2. A CPU has a 16-bit address space, stack pointer initialized to `0x3FF0`, and is executing code at address `0x2050`. An interrupt occurs, causing the CPU to branch to an ISR. The ISR itself is then interrupted by a higher-priority interrupt at ISR address `0x5010`. Draw a diagram of the stack memory showing all pushed values and register contents (PC, SP) at the peak of the nested interrupts.

8.4 Viva Voce Questions

1. "What is the difference between a software interrupt instruction (e.g. INT) and a standard subroutine call (e.g. CALL)?" Model Answer: A `CALL` instruction only saves the return address (PC) on the stack and branches to a user-defined subroutine address within the program space. An `INT` instruction (software interrupt) saves both the PC and the PSW flags, disables interrupts (clearing the IE flag to prevent conflicts), and branches via the Interrupt Vector Table (IVT) to an operating system service routine.
2. "Why do processors decrement the Stack Pointer before writing to stack memory?" Model Answer: This is the convention of a downward-growing stack. The Stack Pointer (SP) points to the current active data byte at the top of the stack. To write new data, the CPU must first decrement SP to point to the next free memory location, then write the data byte.