1.7 Formats & Addressing Modes

An instruction set architecture defines the interface between hardware and software. This chapter explores instruction word formats (3-address, 2-address, 1-address, and 0-address), details the 9 standard addressing modes with a unified memory tracing diagram, defines the mathematical formulas for Effective Address (EA) calculations, and analyzes how addressing modes map to high-level code structures.

Learning Objectives

Identify and list the components of a machine instruction word (opcode, operand addresses, mode bit).
Explain the mathematical effective address (EA) formulas for Immediate, Direct, Indirect, Register Indirect, Indexed, and Relative addressing modes.
Compute arithmetic expressions using instruction sequences for 3-address, 2-address, 1-address (accumulator), and 0-address (stack) computer architectures.
Contrast the memory reference overhead and address space flexibility of direct addressing vs. indirect addressing modes.
Select the most appropriate addressing modes for traversing high-level programming constructs (such as arrays, pointers, and stack parameters).

Prerequisites

Before studying this chapter, you should review Chapter 1.3: Register Organization and Chapter 1.6: Instruction Cycle.

1. Anatomy of an Instruction Word

A machine instruction is a binary word of fixed or variable length. It contains fields that specify the operation to perform and where to locate the operands. The standard partitions are:

Opcode (Operation Code): Identifies the operation (e.g. ADD, SUB, JMP). An $M$-bit opcode can represent $2^M$ distinct operations.
Operand Fields: Contains immediate values, register identifiers, or memory addresses.
Mode Bit: Specifies which addressing mode to use to calculate the effective address of the operand.

2. Instruction Formats

Computers are classified based on the maximum number of operand addresses included in their standard instructions:

3-Address Format: Specifies two source operands and one destination.
ADD Destination, Source1, Source2
Pros: Shortest code length; expressions require few instructions. Cons: Long instruction words requiring many address bits.
2-Address Format: One operand acts as both a source and the destination.
ADD Destination/Source1, Source2
Pros: Shorter instruction words. Cons: Overwrites one of the source operands.
1-Address Format (Accumulator-Based): The CPU has a single implicit register called the Accumulator (AC). The instruction specifies only one memory operand; the other operand and the destination are implicitly the AC.
ADD Address
RTL: $\text{AC} \leftarrow \text{AC} + \text{Memory}[\text{Address}]$.
0-Address Format (Stack-Based): The CPU has an implicit stack memory. Instructions specify only an opcode (e.g. `ADD`). The ALU pops the top two values off the stack, performs the operation, and pushes the result back onto the stack.
ADD

3. The Nine Addressing Modes

To allow programmers flexibility in referencing operands, CPUs implement different addressing modes. The **Effective Address (EA)** is the actual physical address of the operand in memory or register index.

To make the differences easy to grasp, let's trace the modes using a **unified memory and register layout**:

[Figure 1.7.1: Unified Memory Addressing Layout]

  Registers:            Memory Address | Data Value  | Notes
  ┌──────────┬─────┐    ───────────────┼─────────────┼──────────────
  │ R1       │ 400 │    0x0200         │    0x0400   │ Target memory A
  ├──────────┼─────┤    ...            │             │
  │ PC       │ 200 │    0x0300         │    0x000F   │ Data value
  ├──────────┼─────┤    0x0400         │    0x0300   │ Operand address
  │ IX       │ 100 │    ...            │             │
  ├──────────┼─────┤    0x0500         │    0x00FF   │ Operand value
  │ SP       │ 990 │    ...            │             │
  └──────────┴─────┘    0x0990         │    0x000A   │ Top of stack

Figure 1.7.1: Reusable system memory and register map to trace effective address calculations.

3.1 Mode Definitions and EA Math

Immediate Mode: The operand is specified directly in the instruction word itself. No memory reads. $$EA = \text{Instruction Address Field (Value)}$$ Using Figure 1.7.1: Operand value is the field itself (e.g. `#15` $\rightarrow$ value is $15$).
Direct (Absolute) Mode: The instruction address field contains the effective address of the operand in memory. $$EA = A$$ Using Figure 1.7.1 (for $A = 0x0200$): $EA = 0x0200$. $\text{Operand Value} = \text{Memory}[0x0200] = 0x0400$.
Indirect Mode: The address field contains a pointer to the address where the operand is stored. Requires two memory accesses. $$EA = [A]$$ Using Figure 1.7.1 (for $A = 0x0200$): $EA = \text{Memory}[0x0200] = 0x0400$. $\text{Operand Value} = \text{Memory}[0x0400] = 0x0300$.
Register Direct Mode: The operand is stored in an internal CPU register. No memory reads. $$EA = R$$ Using Figure 1.7.1 (for $R = R1$): $\text{Operand Value} = \text{R1} = 400$.
Register Indirect Mode: The designated register holds the memory address of the operand. $$EA = [R]$$ Using Figure 1.7.1 (for $R = R1$): $EA = \text{R1} = 400$. $\text{Operand Value} = \text{Memory}[400] = 0x0300$.
Indexed Mode: The effective address is the sum of the instruction address field $A$ and the contents of the Index Register ($IX$). $$EA = A + [IX]$$ Using Figure 1.7.1 (for $A = 0x0400$): $EA = 0x0400 + \text{IX} = 0x0400 + 100 = 0x0500$. $\text{Operand Value} = \text{Memory}[0x0500] = 0x00FF$.
Relative (PC-Relative) Mode: The effective address is calculated by adding the address field displacement value $A$ to the Program Counter (PC). $$EA = [PC] + A$$ Using Figure 1.7.1 (for $A = 0x0200$): $EA = \text{PC} + 0x0200 = 200 + 512 = 712$.
Stack Mode: The operand is implicitly at the top of the stack pointed to by the Stack Pointer (SP). $$EA = [SP]$$ Using Figure 1.7.1: $EA = 990$. $\text{Operand Value} = \text{Memory}[990] = 0x000A$.

4. Comprehensive Solved Examples

Formats Example 1.7.1

Expression Compilation across Formats

Problem: Write the assembly code sequences to evaluate the arithmetic expression $X = (A + B) \times (C + D)$ using 3-address, 2-address, 1-address (accumulator), and 0-address (stack) formats. (Variables $A, B, C, D, X$ reside in memory).

Solution:

3-Address Format

  ADD T1, A, B    ; T1 = A + B
  ADD T2, C, D    ; T2 = C + D
  MUL X, T1, T2   ; X = T1 * T2

2-Address Format

  MOV T1, A       ; T1 = A
  ADD T1, B       ; T1 = T1 + B (T1 = A + B)
  MOV T2, C       ; T2 = C
  ADD T2, D       ; T2 = T2 + D (T2 = C + D)
  MUL T1, T2      ; T1 = T1 * T2
  MOV X, T1       ; X = T1

1-Address Format (Accumulator)

  LOAD A          ; AC = A
  ADD B           ; AC = AC + B (AC = A + B)
  STORE T1        ; T1 = AC
  LOAD C          ; AC = C
  ADD D           ; AC = AC + D (AC = C + D)
  MUL T1          ; AC = AC * T1
  STORE X         ; X = AC

0-Address Format (Stack)

  PUSH A          ; Stack: A
  PUSH B          ; Stack: B, A
  ADD             ; Stack: (A+B)
  PUSH C          ; Stack: C, (A+B)
  PUSH D          ; Stack: D, C, (A+B)
  ADD             ; Stack: (C+D), (A+B)
  MUL             ; Stack: (A+B)*(C+D)
  POP X           ; X = Stack top

Modes Example 1.7.2

Effective Address and Operand Verification

Problem: Given the memory and register state from Figure 1.7.1, determine the Effective Address ($EA$) and the final operand value loaded for the following instruction configuration: `LOAD [Address/Register]` with address field operand **`0x0200`** using:

(a) Direct Addressing
(b) Indirect Addressing
(c) Indexed Addressing
(d) Register Indirect (for R1)

Solution:

(a) Direct Addressing: - Formula: $EA = A = 0x0200$. - Operand Value: $\text{Memory}[0x0200] = 0x0400$.
(b) Indirect Addressing: - Formula: $EA = [\text{Memory}[A]] = \text{Memory}[0x0200] = 0x0400$. - Operand Value: $\text{Memory}[0x0400] = 0x0300$.
(c) Indexed Addressing: - Formula: $EA = A + [IX] = 0x0200 + 100 = 0x0200 + 0x0064 = 0x0264$.
(d) Register Indirect (for R1): - Formula: $EA = [R1] = 400$ ($0x0190$). - Operand Value: $\text{Memory}[400] = 0x0300$.

5. Core Comparison Tables

Table 1.7.3: Addressing Modes Summary

Mode	EA Formula	Memory Reads	Primary Application
Immediate	$EA = \text{Instruction}$	0	Loading constants.
Direct	$EA = A$	1	Accessing global variables.
Indirect	$EA = [A]$	2	Pointers, passing arguments by reference.
Register Indirect	$EA = [R]$	1	Pointer arithmetic in loops.
Indexed	$EA = A + [IX]$	1	Array traversal ($A$ is array base, $IX$ is index).

6. Common Mistakes Students Make

Common Pitfalls & Cognitive Traps

Confusing the Effective Address ($EA$) with the Operand Value: Students frequently calculate the address correctly but write it down as the operand value itself. The $EA$ is only the *location* pointer; a final memory/register read must be executed to copy the actual value.
Underestimating Indirect Addressing Overhead: When asked how many memory references are made by an indirect instruction (e.g. `ADD @200`), students often say one. Remember: the CPU must first read memory at `200` to get the target address, then read memory a *second* time at the target address to get the operand.
Miscalculating PC-Relative branch offsets: During exam traces, students often compute PC-relative branches from the *current* instruction's address. Remember: the PC is already incremented during the fetch cycle (pointing to the *next* instruction) before the relative offset is added.
Stack Pointer Direction Mistakes: Pushing onto the stack decrements SP, whereas popping increments SP. When writing stack addressing expressions, students often get the sign changes reversed.

🎯 Key Takeaways

An **instruction format** dictates the number of address fields. Layouts include 3, 2, 1 (AC-based), and 0 (stack-based) address formats.
The **Effective Address (EA)** is the physical location of the operand.
**Immediate** and **Register Direct** modes require $0$ memory reads. **Direct** and **Register Indirect** modes require $1$ memory read. **Indirect** mode requires $2$ memory reads.
**Indexed addressing** ($EA = A + [IX]$) is physically optimized for array offsets. **Base-displacement addressing** is optimized for local variables in stack frames.

🔗 Connection to Future Chapters

The instruction formats and stack/relative addressing modes defined here serve as the instruction set foundation for **Chapter 4.1** (RISC vs. CISC architectures) and **Chapter 4.2** (pipelining).

7. Assessment Bank

7.1 Multiple Choice Questions

Q1. Under which addressing mode is the Effective Address of the operand calculated as $EA = A + [IX]$?

Q2. How many memory reads (excluding the instruction fetch cycle itself) are required to execute a `LOAD` instruction using Indirect Addressing mode?

Q3. An accumulator-based computer uses which instruction format representation?

Q4. Which addressing mode is best suited for referencing local variables inside a subroutine stack frame?

7.2 Short Answer Questions

Trace the difference between Register Direct and Register Indirect addressing modes. How many memory accesses does each require?
Write the assembly instruction formats (3, 2, 1, 0 addresses) to evaluate the operation $Y = A + B$.
What is the role of the Mode Bit in an instruction word?

7.3 Long Answer / Exam Questions

An instruction at address `0x0100` is `LOAD 0x0050` (using relative addressing). If $PC = 0x0102$, memory location `0x0152` contains value `0x5000`, and memory location `0x0050` contains `0x2000`: - (a) Calculate the Effective Address ($EA$) if the instruction uses Direct, PC-Relative, and Indirect addressing modes. - (b) Trace the operand value loaded into the CPU for each mode.
Discuss the architectural and performance differences between accumulator-based CPUs (1-address) and stack-based CPUs (0-address). Compare code density, execution speed, and instruction sizes.

7.4 Viva Voce Questions

"Why do PC-relative branch offsets in assembly instructions use signed displacements?" Model Answer: Because a branch can go forward (positive displacement) or backward (negative displacement) in memory relative to the Program Counter. A signed integer allows branching in both directions.
"What is auto-increment and auto-decrement addressing, and when are they used?" Model Answer: In these modes, the register containing the address of the operand is automatically incremented or decremented by the size of the operand after (or before) execution. They are physically used to implement stack pushes/pops and fast loop increments during block data copies.