2.3 Hardwired Control Unit

The Control Unit (CU) coordinates all activities inside the CPU by issuing timing-aligned control signals. This chapter covers the hardware structure of a Hardwired Control Unit. We analyze opcode decoders, sequence counters generating clock states ($T_i$), logic gate array synthesis, and compare hardwired and microprogrammed architectures.

Learning Objectives

Identify the hardware components of a Hardwired Control Unit (Sequence Counter, Decoders, Logic Gates).
Explain how opcode decoders and sequence counters generate timing states ($T_i$) and instruction indicators ($D_i$) simultaneously.
Construct Boolean logic control expressions for hardware control signals (e.g. read, write, load) given a set of register transfers.
Contrast hardwired control units with microprogrammed control units in terms of speed, flexibility, and design complexity.
Evaluate the cost/performance trade-offs of expanding instruction sets on a hardwired control processor.

Prerequisites

Before studying this chapter, you must understand Chapter 1.6: Instruction Cycle & Interrupts to understand how instruction cycles are partitioned into sequential clock steps.

1. Introduction to Control Organization

To execute any microoperation, the control unit must assert a corresponding physical control wire (e.g., triggering register load pins, opening bus multiplexers, or selecting ALU operation codes). There are two fundamental ways to generate these control signals:

Hardwired Control: Control signals are generated using physical logic gates, decoders, and counter logic arrays. This offers maximum operating speeds but is highly rigid to design modifications.
Microprogrammed Control: Control signals are stored as binary words (microinstructions) in a dedicated Control Memory (ROM) and read sequentially. This offers high flexibility but introduces memory access delays.

2. Structure of a Hardwired Control Unit

A typical hardwired control unit consists of three hardware components:

Instruction Register (IR) Decoders: - The IR holds the fetched instruction. - The 3-bit Opcode field (bits 12-14) connects to a $3 \times 8$ decoder, generating active-high signals $D_0$ through $D_7$. - Bit 15 represents the addressing mode indicator ($I$).
Sequence Counter (SC) and Decoder: - The SC is a 4-bit binary counter driven by the master CPU clock. - The counter outputs are decoded by a $4 \times 16$ decoder, generating timing signals $T_0$ through $T_{15}$ sequentially. - SC features a Clear input (CLR) to reset timing back to $T_0$, ensuring instructions that complete execution in fewer than 16 cycles do not waste timing slots.
Control Logic Gate Array: - An array of AND/OR gates that combines the decoded signals ($D_i, T_i$) and status flags (e.g. Zero, Sign, Carry) to assert specific control outputs.

[Figure 2.3.1: Hardwired Control Unit Architecture]

  [ Instruction Register (IR) ]
        │ (bits 12-14)       │ (bit 15)
        ▼                    ▼
  [ 3x8 Decoder ]        [ Mode Bit I ]
        │ D_0 - D_7          │
        ▼                    ▼
  ┌──────────────────────────────────────────────┐
  │         Control Logic Gate Array             │ ──► Control Outputs
  └──────────────────────────────────────────────┘     (Load, Read, Write)
        ▲
        │ T_0 - T_15
  [ 4x16 Decoder ]
        ▲
  [ 4-bit Sequence Counter (SC) ] ◄── Clock & Clear (CLR_SC)

Figure 2.3.1: Hardware block diagram showing the interaction of the IR, opcode decoder, sequence counter, and control gates.

3. Control Logic Synthesis

To synthesize the logic gates for a specific control line, we write the Boolean sum-of-products equation by gathering all instruction-timing combinations where that line must be high.

3.1 Memory WRITE Control Signal

Suppose the CPU writes data to Memory during:

The store accumulator instruction (`STA` decoded as $D_3$) at timing state $T_5$: $D_3 T_5$.
The increment and skip if zero instruction (`ISZ` decoded as $D_5$) at timing state $T_6$: $D_5 T_6$.
The interrupt return phase (timing signal $r T_2$): $r T_2$.

The synthesized logic equation for the memory `WRITE` line is: $$\text{WRITE} = D_3 T_5 + D_5 T_6 + r T_2$$

3.2 Sequence Counter Clear ($CLR_{SC}$) Control Signal

To ensure the sequencer returns to $T_0$ immediately after executing an instruction, we must clear the SC. For example, if a store accumulator (`STA` $D_3$) finishes execution at timing state $T_5$, we assert $CLR_{SC}$: $$CLR_{SC} = D_3 T_5 + D_4 T_6 + r T_3$$

4. Worked Examples

Synthesis Example 2.3.1

Synthesizing Memory READ Logic

Problem: A basic computer asserts the memory `READ` control line during the following states: - Fetch cycle: timing states $T_0$ and $T_1$. - Indirect address calculation: timing state $T_2$ when the mode bit $I = 1$. - Memory-reference instructions: `AND` ($D_0 T_4$) and `ADD` ($D_1 T_4$). Write the synthesized Boolean expression for the `READ` control output.

Solution:

Identify the logic terms for each condition: - Fetch: $T_0 + T_1$ - Indirect address: $I T_2$ (asserts only when indirect bit $I$ is high at state $T_2$) - Memory-read instructions: $D_0 T_4 + D_1 T_4$
Combine the terms using OR logic: $$\text{READ} = T_0 + T_1 + I T_2 + D_0 T_4 + D_1 T_4$$

Answer: The synthesized equation is **$\text{READ} = T_0 + T_1 + I T_2 + D_0 T_4 + D_1 T_4$**.

5. Hardwired vs. Microprogrammed Control Comparison

Selecting a control unit design model is a critical trade-off in computer architecture. We contrast the features of both:

Table 2.3.2: Comparison Matrix

Characteristic	Hardwired Control Unit	Microprogrammed Control Unit
Operating Speed	Very Fast (limited only by gate propagation delays).	Slower (requires control memory read cycles).
Modification Flexibility	Very Low (requires physical rewiring of logic gates).	High (requires updating microprograms in ROM).
Instruction Set Complexity	Suited for RISC (simple, uniform instruction sets).	Suited for CISC (complex, variable-length instructions).
Hardware Cost	Low for simple architectures; grows exponentially with instruction counts.	Higher initial cost (requires ROM arrays, CAR/CDR registers).

6. Common Mistakes Students Make

Common Pitfalls & Cognitive Traps

Assuming every instruction takes 16 timing states: Because the Sequence Counter generates timing states $T_0$ to $T_{15}$, students think every cycle is 16 states long. In reality, the control logic triggers the SC Clear pin ($CLR_{SC}$) as soon as the active execute cycle completes, resetting timing back to $T_0$ (e.g. at $T_5$).
Confusing Opcode Decoders with SC Decoders: When analyzing logic gates, students often mix up opcodes ($D_i$) and timing states ($T_i$). Remember: opcodes identify *what* operation to perform, while timing states identify *when* to execute each register transfer step. Both must be AND-ed together.

🎯 Key Takeaways

A Hardwired Control Unit uses **opcode decoders**, **sequence counters**, and **logic gate arrays** to generate control signals.
The Sequence Counter (SC) resets to $T_0$ using the $CLR_{SC}$ control pin, optimizing timing cycles.
We synthesize control line logic equations by combining active-high opcodes and timing triggers.
Hardwired controllers offer maximum execution speeds at the expense of zero design flexibility.

🔗 Connection to Next Chapter

To overcome the inflexibility of hardwired gate arrays, we can store control signals as microprograms in memory. Proceed to **Chapter 2.4: Control Memory & Address Sequencing** to study microprogrammed controller hardware.

7. Assessment Bank

7.1 Multiple Choice Questions

Q1. What hardware component is responsible for generating timing states ($T_0$ through $T_{15}$) inside a hardwired control unit?

Q2. Why are hardwired control units favored in RISC processors over CISC processors?

7.2 Short Answer Questions

How does the Sequence Counter clear pin ($CLR_{SC}$) optimize processor performance?
Write the Boolean control expression for a register load line that asserts during instruction $D_4$ at $T_5$ and instruction $D_7$ at $T_4$.

7.3 Long Answer Questions

A processor has 8 timing states ($T_0$ to $T_7$) and 16 instructions ($D_0$ to $D_{15}$). Design the decoder hardware block required for the sequence counter and instruction registers. Draw the schematic.
Contrast Hardwired and Microprogrammed Control Units. Analyze their timing delays, hardware footprints, design flexibility, and suitability for RISC and CISC architectures.