2.4 Control Memory & Address Sequencing

Microprogrammed Control Units store control configurations as software routines in memory. This chapter covers the hardware structure of the microprogrammed controller. We analyze the Control Memory (ROM), the Control Address Register (CAR), the Control Data Register (CDR), and the Address Sequencer's next-address multiplexing logic.

Learning Objectives

Define the roles of Control Memory, Control Address Register (CAR), and Control Data Register (CDR) in a microprogrammed control unit.
Explain how the address sequencer selects the next microinstruction address from incrementing, branching, mapping, or return inputs.
Compute target Control Memory addresses using instruction mapping logic (e.g., prefixing/suffixing zero bits to opcodes).
Contrast microinstruction sequencing options (such as conditional branching, mapping, and subroutine calls) in terms of sequencer multiplexer inputs.
Evaluate the impact of microprogram subroutine support on the complexity of the address sequencer hardware.

Prerequisites

Before studying this chapter, you must understand Chapter 2.3: Hardwired Control Unit to contrast hardwired gate arrays with memory-driven control pipelines.

1. Foundations of Microprogrammed Control

A microprogrammed control unit operates by executing a sequence of low-level hardware instructions, known as **microinstructions**, stored in a internal memory block called the Control Memory (ROM).

Each microinstruction contains:

A set of control bits that directly connect to hardware enable lines (ALU codes, register loads, bus selectors).
Address sequencing fields that determine the location of the *next* microinstruction to execute.

2. Core Sequencer Registers

To coordinate microprogram execution, the sequencer contains three registers:

Control Address Register (CAR): - Analogous to the Program Counter (PC) in main memory. - Holds the address of the microinstruction currently being read from Control Memory.
Control Data Register (CDR): - Holds the microinstruction word currently being executed. - Decoded control bits are held in the CDR to stabilize control lines during clock phases.
Subroutine Register (SBR): - Holds return addresses when a microprogram calls a subroutine (e.g. returning from an indirect addressing fetch routine).

[Figure 2.4.1: Sequencer Address Flow loop]

  ┌──────────────────────────────────────────────────────────┐
  │                                                          │
  ▼                                                          │
[ Control Address Register (CAR) ]                           │
  │                                                          │
  ▼                                                          │
[ Control Memory (ROM) ]                                     │
  │                                                          │
  ▼                                                          │
[ Control Data Register (CDR) ]                              │
  │                                                          │
  ├─► Control Signals (ALU, registers, bus)                  │
  │                                                          │
  ▼ (Next Address fields)                                    │
[ Address Sequencer (MUX paths) ] ───────────────────────────┘
  ▲         ▲         ▲
  │         │         │
[ SBR ]  [ Map ]  [ Incrementer ]

Figure 2.4.1: Schematic representation of the microprogrammed Control Address loop.

3. Address Sequencing & Multiplexer Paths

The **Address Sequencer** is the logic block that determines the next address to load into the CAR. Under the control of the select lines ($S_1, S_0$) derived from the microinstruction's branch ($BR$) field, the sequencer multiplexer selects among four sources:

Increment (INC): Selects $CAR + 1$. This executes sequential microinstructions in a routine.
Branch (BR / ADR): Selects the address field ($AD$) of the current microinstruction, executing a jump if conditional checks succeed.
Instruction Mapping (MAP): Converts a fetched macroinstruction opcode into the starting address of its microprogram routine in Control Memory.
Return (RET): Loads the SBR contents back into the CAR, returning from a micro-subroutine.

3.1 Instruction Mapping Logic

When a macroinstruction is fetched, the opcode must be mapped to a Control Memory address. Suppose the opcode is 4 bits: $OP = OP_3 OP_2 OP_1 OP_0$.

To allow up to 4 microinstructions per routine, the mapping logic prefixes a 0 and suffixes two 0s to the opcode: $$\text{CAR Address} = 0\ OP_3\ OP_2\ OP_1\ OP_0\ 0\ 0_2$$ This transforms a 4-bit opcode into a 7-bit Control Address.

4. Worked Examples

Mapping Example 2.4.1

Opcode-to-Address Mapping Math

Problem: A processor utilizes a 5-bit opcode field. The control memory address mapping logic is configured to prefix a 0 and suffix three 0s to the opcode. 1. Calculate the size of the Control Address Register (CAR). 2. Determine the mapped Control Memory starting address (in binary and hexadecimal) for opcode `11010`. 3. How many microinstructions can be stored in each opcode routine?

Solution:

Determine CAR size: Mapping structure: $0 \ (1\text{ bit}) + \text{Opcode} \ (5\text{ bits}) + 000 \ (3\text{ bits}) = 9\text{ bits}$. Therefore, the CAR must be **9 bits** wide.
Determine Mapped Address: Opcode: `11010` Mapped: `0` (prefix) + `11010` (opcode) + `000` (suffix) = `011010000` Hexadecimal conversion: `0110 1000 02` = `0x0D0`.
Calculate Routine Capacity: Because we suffixed 3 zero bits, each routine is allocated $2^3 = 8$ addresses. Therefore, each routine can hold up to **8 microinstructions**.

5. Core Comparison Tables

Table 2.4.2: Address Sequencer Multiplexer Selector Matrix

S1	S0	Selected Source	Register Operation	Typical Instruction Usage
0	0	Incrementer	$CAR \leftarrow CAR + 1$	Sequential execution
0	1	Current ADR	$CAR \leftarrow ADR$	Unconditional or conditional branching
1	0	Mapping Logic	$CAR \leftarrow Mapping(Opcode)$	Instruction decode and branch to routine
1	1	Subroutine SBR	$CAR \leftarrow SBR$	Returning from subroutines (RET)

6. Common Mistakes Students Make

Common Pitfalls & Cognitive Traps

Confusing CAR and PC: Students often state that the Program Counter (PC) points to the next microinstruction. This is incorrect. The PC points to macroinstructions in the external RAM, while the CAR points to microinstructions inside the internal Control ROM.
Assuming Mapping Logic resets the SBR: During an instruction mapping branch ($CAR \leftarrow Mapping(Opcode)$), students frequently assume the SBR register is loaded with the old CAR. This is incorrect; mapping logic is a simple jump, not a subroutine call. The SBR is only loaded during an explicit subroutine call instruction.

🎯 Key Takeaways

**Control Memory (ROM)** stores all microprograms that dictate processor control operations.
The **Control Address Register (CAR)** holds the address of the active microinstruction.
The **Address Sequencer** multiplexer selects the next control address using four modes: Increment, Branch, Map, and Return.
Instruction Mapping converts opcodes to control addresses by prefixing and suffixing zero bits.

🔗 Connection to Next Chapter

Now that we have analyzed the address sequencing logic, we can construct the actual fields of a microinstruction. Proceed to **Chapter 2.5: Control Unit Design** to study microoperation field decoding and write complete microprogram routines.

7. Assessment Bank

7.1 Multiple Choice Questions

Q1. Which register is responsible for holding return addresses during micro-subroutine calls?

Q2. What mapped 8-bit Control Memory address is generated for a 4-bit opcode `1011` if the mapping scheme prefixes a 0 and suffixes three 0s?

7.2 Short Answer Questions

Describe the functional difference between the PC and the CAR.
Explain the four address sources routed into the Address Sequencer multiplexer.

7.3 Long Answer Questions

Design a custom address sequencer multiplexer circuit. Sketch the block diagram showing the CAR, SBR, mapping block, and control input selectors.