2.5 Control Unit Design

Designing a microprogrammed control unit requires formulating the microinstruction bit layouts and implementing the decoders that map control fields to physical signals. This chapter details microinstruction formatting, groups mutually exclusive microoperations into control fields, and presents a complete worked microprogram executing Fetch, Indirect, and ADD routines.

Learning Objectives

Define the differences between horizontal (unencoded) and vertical (highly encoded) microinstruction formats.
Explain how control field bits in a microinstruction are decoded by external decoders to activate specific control gates.
Write a complete microprogrammed Fetch routine and instruction execution routine (e.g. ADD) using symbolic microassembly code.
Contrast horizontal and vertical microinstruction formats in terms of control memory width, decoding speed, and flexibility.
Evaluate the impact of status bit selection (carry, sign, zero) on conditional branching logic within a microprogrammed Control Unit.

Prerequisites

Before studying this chapter, you must understand Chapter 2.4: Control Memory & Address Sequencing to understand next-address sequencing multiplexers.

1. Microinstruction Format Specifications [Pending Verification]

A microinstruction consists of fields that specify one or more microoperations, select status bit conditions, select next-address modes, and provide target branch addresses.

Under the canonical Mano design framework, a **20-bit microinstruction** is partitioned into six fields:

  ┌───────────┬───────────┬───────────┬──────────┬──────────┬─────────────────┐

  │ F1 (3b)   │ F2 (3b)   │ F3 (3b)   │ CD (2b)  │ BR (2b)  │ AD Address (7b) │

  └───────────┴───────────┴───────────┴──────────┴──────────┴─────────────────┘

$F_1, $F_2, $F_3$ (Microoperation Fields): 3 bits each. Group mutually exclusive operations. E.g. field $F_1$ decodes to commands like `ADD` or `CLE`, while $F_2$ decodes to `SUB` or `LDA`. Because they are mutually exclusive, a maximum of 3 microoperations can be declared in a single microinstruction.
$CD$ (Condition Select Field): 2 bits. Selects status conditions:
- `00` ⇒ Unconditional branch.
- `01` ⇒ Check mode bit ($I$).
- `10` ⇒ Check Sign flag ($S$).
- `11` ⇒ Check Zero flag ($Z$).
$BR$ (Branch Field): 2 bits. Selects next-address sequencing:
- `00` ⇒ Jump (`JMP`).
- `01` ⇒ Call subroutine (`CALL`).
- `10` ⇒ Return from subroutine (`RET`).
- `11` ⇒ Map instruction opcode (`MAP`).
$AD$ (Control Address Field): 7 bits. Holds the branch address.

2. Horizontal vs. Vertical Microinstructions [Pending Verification]

Microprogrammed architectures are classified by how control fields are encoded inside microinstructions:

Horizontal Microinstructions: - Every control signal in the processor is allocated a dedicated bit. - No decoders are needed; bits directly connect to control wires. - **Strengths**: Maximum operating speed. - **Weaknesses**: Wide control words (e.g. 50-100 bits), requiring large control memories.
Vertical Microinstructions: - Control signals are highly encoded into fields. - Requires decoders to decode binary codes into control signals. - **Strengths**: Narrow control words (e.g. 16-24 bits), saving memory space. - **Weaknesses**: Slower operating speed due to decoder propagation delays.

3. Complete Worked Microprogram [Pending Verification]

To illustrate control execution, we present a complete microprogram routine implementing Fetch, Indirect address fetch, and ADD execution:

3.1 Micro-Fetch Routine

The macro-Fetch phase executes in four sequential microinstructions:

                            T0: MAR ◄─ PC           (F1 = 010: PC to bus, F2 = 001: load MAR)

                            T1: MDR ◄─ M[MAR]       (F3 = 100: memory read, F2 = 010: load MDR)

                            T2: IR  ◄─ MDR          (F1 = 100: MDR to bus, F2 = 100: load IR)

                            T3: PC  ◄─ PC + 1       (F1 = 101: increment PC, BR = 11: MAP to execution)

3.2 Micro-Indirect Address Routine

If the instruction mode bit $I = 1$, the processor branches to the Indirect routine to fetch the operand address:

                            T3: MAR ◄─ MDR[AD]      (F1 = 110: load address portion, BR = 00: JMP back)
                        

3.3 Micro-ADD Routine

The execution phase for addition:

                            T4: AC  ◄─ AC + DR       (F1 = 001: ALU ADD, F2 = 101: load AC, BR = 00: JMP to Fetch)
                        

4. Worked Examples

Encoding Example 2.5.1

Symbolic to Binary Microinstruction Translation

Problem: Translate the symbolic microinstruction: `ADD, CD = U, BR = JMP, AD = 0x3F` into its 20-bit binary equivalent under the Mano framework (where `ADD` code is F1=001, Unconditional condition U is CD=00, and JMP is BR=00).

Solution:

Determine control fields values: - $F_1 = 001$ (`ADD` active). - $F_2 = 000$ (no operation). - $F_3 = 000$ (no operation). - $CD = 00$ (unconditional check). - $BR = 00$ (`JMP` branch mode). - $AD = 0111111_2$ (7-bit representation of `0x3F`).
Concatenate binary fields: `001` + `000` + `000` + `00` + `00` + `0111111` = `00100000000000111111`

Answer: The binary microinstruction is **`00100000000000111111`**.

5. Core Comparison Tables [Pending Verification]

Table 2.5.2: Horizontal vs. Vertical Architecture

Feature	Horizontal Format	Vertical Format
Width	Wide (e.g. 48-128 bits).	Narrow (e.g. 16-24 bits).
Decoders	None (direct gating).	Required (F1, F2, F3 field decoders).
Speed	Fast (no decoding delay).	Slower (propagation delays through decoders).
Concurrency	High (many operations per cycle).	Low (limited by field partitions).

6. Common Mistakes Students Make

Common Pitfalls & Cognitive Traps

Attempting conflicting operations: Students often try to execute two operations from the same field (e.g. setting $F_1$ to both load AC and increment AC in a single microinstruction). Because each field connects to a single $3\times8$ decoder, only one output line can be active per cycle. Conflicting operations must be placed in different clock cycles.
Confusing microoperation symbols with macroinstructions: When writing microprograms, students confuse symbolic register transfers (e.g. `ADD` in $F_1$) with the assembly instruction `ADD`. Micro-ADD is a basic control code that triggers the ALU adder, while macro-ADD is a full memory-reference instruction involving fetch and decode.

🎯 Key Takeaways

A microinstruction format is partitioned into **microoperations ($F_1, F_2, F_3$)**, **condition ($CD$)**, **branch ($BR$)**, and **address ($AD$)** fields.
**Horizontal microprogramming** offers maximum execution speed at the expense of wide control words.
**Vertical microprogramming** reduces width using field decoders but introduces decoding delays.
A microprogrammed instruction routine begins with a **Fetch cycle** that loads the macroinstruction from RAM.

🔗 Connection to Next Unit (Unit III)

Now that we have designed the processor and control organization, we must analyze memory connections and RAM/ROM address maps. Proceed to **Chapter 3.1: Memory Decoding** in Unit III to study memory interfacing.

7. Assessment Bank

7.1 Multiple Choice Questions

Q1. Under vertical microprogramming, how many active control outputs can be generated simultaneously from a single 3-bit microoperation field ($F_1$)?

Q2. What field is evaluated to decide next-address selection if $BR = 01$ (CALL)?

7.2 Short Answer Questions

Contrast horizontal and vertical microprogram formats in terms of speed and size.
Write the microinstructions required to execute the Fetch phase.

7.3 Long Answer Questions

Design the decoding hardware for a microprogrammed control unit. Sketch the schematics showing three $3\times8$ decoders and control gates generating load AC, write memory, and clear PC signals.