3.6 I/O Interface

While the processor interfaces directly with high-speed memory using unified buses, peripherals exhibit speed, data format, and voltage level mismatches. The system implements I/O Interface cards to bridge this connection. This chapter explores peripheral device interface structures, Memory-Mapped vs. Isolated I/O configurations, and control signals.

Learning Objectives

Define terminology: Peripheral, I/O Interface, Port, Memory-Mapped I/O, Isolated I/O, and status flags.
Explain why CPU buses cannot directly connect to peripheral devices without interface cards.
Construct control logic to select an I/O device port based on address bus lines and isolated I/O control lines.
Contrast Memory-Mapped I/O and Isolated (I/O Mapped) I/O in terms of address space allocation, assembly instructions, and control signals.
Evaluate the design trade-off of dedicating a portion of memory addresses to I/O ports in memory-mapped structures.

Prerequisites

Before studying this chapter, you should review Chapter 3.5: Virtual Memory & Paging to understand logical page translations and hardware memory interfaces.

1. The Mismatch Between CPU and Peripherals

Peripherals cannot connect directly to CPU system buses due to three primary mismatches:

**Speed Mismatch**: CPU operates at gigahertz speeds, whereas electromechanical peripherals (disk drives, printers) operate at milliseconds speeds.
**Format Mismatch**: Peripherals often transmit data serially, whereas the CPU bus requires parallel data formats.
**Voltage/Signal Mismatch**: Peripherals operate under varying electrical standards that are incompatible with CPU TTL logic levels.

2. Structure of a Typical I/O Interface Card

To bridge this mismatch, an **IO Module** (or I/O Interface card) is placed between the system bus and the device. An interface features four internal registers (ports):

**Data Input Buffer**: Stores incoming byte streams from the device.
**Data Output Buffer**: Stores outgoing byte streams to the device.
**Status Register**: Holds read-only status flag bits (e.g. Device Busy, Error, Data Ready).
**Control Register**: Receives configuration write commands from the CPU (e.g. set Baud Rate).

3. Memory-Mapped I/O vs. Isolated I/O

Peripherals are addressed using one of two paradigms:

**Memory-Mapped I/O**: - The interface ports are allocated standard addresses in the main memory address space. - Uses memory read ($MEMR$) and memory write ($MEMW$) bus control lines. - Programmed using standard instructions (e.g. `MOV`, `LD`, `ST`).
**Isolated I/O**: - The interface ports occupy a separate, dedicated I/O address space. - Uses dedicated read ($IOR$) and write ($IOW$) bus control lines. - Requires special assembly instructions (e.g. `IN`, `OUT`).

4. Worked Examples & Traces

Execution Trace

Worked Example 3.6.1: Isolated vs. Memory-Mapped Address Decoding

**Problem**: Trace how a 16-bit Address Bus `0xFC03` routes to activate an I/O Port under (a) Memory-Mapped I/O and (b) Isolated I/O.

**Step-by-Step Port Resolution Trace**:

**Deconstruct Address Bus state**: $$\text{Address } \text{0xFC03} = 1111\ 1100\ 0000\ 0011_2$$
**Scenario (a): Memory-Mapped I/O**: - The system decoder detects that the high-order bits $A_{15}-A_8$ are `0xFC`. This matches the reserved I/O address block. - The decoder asserts the **Chip Select ($CS$)** line of the target I/O Interface card. - Low-order bits $A_1, A_0 = 11_2$ select register index $3$ (Control Register) on the card. - When the CPU asserts control line $MEMW$, the data on the Data Bus is written to the interface Control Register.
**Scenario (b): Isolated I/O**: - The address `0xFC03` is placed on the Address Bus. - Memory chips ignore the address because control lines $MEMR$/$MEMW$ remain inactive. - The CPU executes an `OUT` instruction, asserting the dedicated **$IOW$** control bus line. - The I/O Port decoder detects $IOW = 0$ (active-low), matches the port address `0xFC03` on the bus, asserts the card's Chip Select, and writes the Data Bus byte to the internal register.

Viva Voce Q&A

Oral Exam Preparation

**Question**: "What is the primary advantage of Isolated I/O over Memory-Mapped I/O?"

**Answer**: Isolated I/O keeps a separate address space for I/O devices, meaning that I/O ports do not consume main memory addresses. This preserves the entire physical memory address map for RAM and ROM chips.

Common Mistakes to Avoid

Warning: Common Student Pitfalls

**Confusing read/write controls**: Writing standard memory instructions to Isolated I/O ports without using the dedicated `IN`/`OUT` opcodes.
**Forgetting Address Lines**: Assuming that Isolated I/O does not use address lines. It still uses address lines to select port IDs, but uses distinct control signals ($IOR$/$IOW$).

Revision Summary & Takeaways

I/O interfaces bridge speed, format, and voltage differences.
Memory-Mapped I/O shares the memory address space and uses $MEMR$/$MEMW$ control signals.
Isolated I/O uses dedicated port ranges and $IOR$/$IOW$ control signals.

How this chapter connects to the next

We have seen how I/O ports map to physical addresses. In Chapter 3.7: Asynchronous Transfer, we analyze how these interface cards coordinate time-independent transfers using strobe and handshaking waveforms.

Check Your Understanding

1. Which control lines are asserted when writing to a memory-mapped I/O port?

References

**ref-notes-syed-arsalaan**: Handwritten Lecture Notes, Page 94 (I/O Interface Block Diagrams). [Local Verified]
**ref-notes-class**: Class COA Lecture Notes, Page 46 (Memory-Mapped vs. Isolated I/O). [Local Verified]
**ref-book-mano**: M. Morris Mano, *Computer System Architecture*, 3rd Edition, Chapter 11. [Pending Verification]
**ref-lecture-sengupta-30**: Prof. Indranil Sengupta, NPTEL COA, Lecture 30 (I/O Interfacing). [Pending Verification]