3.7 Asynchronous Transfer

While synchronous buses rely on a single system clock to coordinate transfers, asynchronous interfaces connect independent devices operating under separate clock sources. This chapter explores Strobe Control and feedback-driven Handshaking protocols.

Learning Objectives

Define terms: Asynchronous, Strobe, Handshaking, 4-Phase Handshake, Data Valid, and Data Accepted.
Explain the timing vulnerability of Strobe Control (no feedback signal to verify receipt of data).
Sketch the timing diagrams and bus waveforms for Source-Initiated and Destination-Initiated handshaking.
Contrast 2-Phase Handshaking with 4-Phase Handshaking in terms of control overhead and transition counts.
Evaluate the reliability improvement of a double-handshake protocol in high-speed, noisy communication systems.

Prerequisites

Before studying this chapter, you should review Chapter 3.6: I/O Interface to understand data buffers and status/control registers.

1. Foundations of Asynchronous Transfer

In synchronous transfers, a central clock line dictates read/write timings. However, if a peripheral device is slow, the CPU must stall. Asynchronous bus transfers eliminate shared clock lines, executing transfers using point-to-point **Control Bus** signals (Strobe or Request/Acknowledge lines).

2. Strobe Control Protocol

**Strobe Control** utilizes a single control line to signal data validity:

**Source-Initiated Strobe**: The transmitting device places data on the **Data Bus** and, after a propagation delay, asserts a Strobe line. The destination uses the strobe edge to latch the data. - **Vulnerability**: Open-loop system. The source has no confirmation that the destination was ready or successfully latched the data.
**Destination-Initiated Strobe**: The receiving device asserts a Strobe line, signaling it is ready. The source responds by placing data on the bus. - **Vulnerability**: The destination has no verification that the source actually placed data on the bus before the strobe line is deasserted.

3. Handshaking Protocols

**Handshaking** resolves strobe vulnerabilities by adding a feedback control line: - **Request ($REQ$)**: Asserted by the initiator to request a transfer. - **Acknowledge ($ACK$)**: Asserted by the responder to verify data has been read or placed on the bus.

Depending on which unit starts the transfer, we classify handshakes as: - **Source-Initiated Handshake**: Employs Data Valid ($REQ$) and Data Accepted ($ACK$) lines. - **Destination-Initiated Handshake**: Employs Request Data ($REQ$) and Data Valid ($ACK$) lines.

4. The 4-Phase Handshake Sequence

A **4-Phase Handshake** is a fully-interlocked protocol ensuring both units synchronize transitions. The sequence is as follows:

**Phase 1**: Source places data on the Data Bus, then asserts $REQ$ (high).
**Phase 2**: Destination detects $REQ$ high, reads the bus, then asserts $ACK$ (high).
**Phase 3**: Source detects $ACK$ high, removes data from the bus, and deasserts $REQ$ (low).
**Phase 4**: Destination detects $REQ$ low, then deasserts $ACK$ (low). The bus is now reset for the next cycle.

5. Worked Examples & Traces

Execution Trace

Worked Example 3.7.1: 4-Phase Handshake timing transitions

**Problem**: Trace the transition sequence of a source-initiated 4-phase handshake.

**Trace Timeline**:

  1. Source (CPU)    ──► Places data on Data Bus
  2. Source (CPU)    ──► Asserts REQ (High)
  3. Device          ──► Detects REQ High, reads Data Bus
  4. Device          ──► Asserts ACK (High)
  5. Source (CPU)    ──► Detects ACK High, removes data
  6. Source (CPU)    ──► Deasserts REQ (Low)
  7. Device          ──► Detects REQ Low, deasserts ACK (Low)
  8. Cycle Complete  ──► All lines are idle/low

Viva Voce Q&A

Oral Exam Preparation

**Question**: "What is the primary difference between a 2-phase handshake and a 4-phase handshake?"

**Answer**: A **4-phase handshake** is fully interlocked; it requires signal transitions to return to their idle low states before a new transfer can begin, making it extremely reliable. A **2-phase handshake** (or non-interlocked handshake) triggers transfers on any signal transition (high-to-low or low-to-high), which is faster but highly vulnerable to electrical noise.

Common Mistakes to Avoid

Warning: Common Student Pitfalls

**Confusing Strobe and Handshake**: Forgetting that strobe control is open-loop (no feedback line), whereas handshaking uses request/acknowledge feedback lines.
**Timing Skews**: Neglecting the propagation delay required for data signals to stabilize on the bus before control signals are asserted.

Revision Summary & Takeaways

Asynchronous transfers connect units with separate clock sources.
Strobes use a single control line, creating timing vulnerability due to lack of feedback.
Handshaking protocols use request ($REQ$) and acknowledge ($ACK$) lines for closed-loop safety.

How this chapter connects to the next

We have analyzed the bus waveforms used to coordinate asynchronous data transfers. In Chapter 3.8: Modes of Transfer, we elevate our perspective to look at execution paradigms, comparing how the CPU handles this transfer logic using polling or interrupts.

Check Your Understanding

1. In a source-initiated handshake, which signal is asserted by the receiving device to verify data has been latched?

References

**ref-notes-syed-arsalaan**: Handwritten Lecture Notes, Page 97 (4-Phase Handshake). [Local Verified]
**ref-notes-class**: Class COA Lecture Notes, Page 48 (Strobes vs. Handshaking). [Local Verified]
**ref-book-hamacher**: Carl Hamacher, *Computer Organization*, 5th Edition, Chapter 4. [Pending Verification]
**ref-lecture-zilles-8**: Prof. Craig Zilles, Illinois ECE 290, Lecture 8 (Asynchronous Transfers). [Pending Verification]