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3.9 Priority Interrupts

When multiple peripherals assert interrupt requests simultaneously, the system must use hardware priority arbiters to determine which device is serviced first. This chapter explores Daisy Chaining priority lines, Parallel Priority logic, and Priority Encoder circuit designs.

Learning Objectives

  • Define terms: Priority Interrupt, Daisy Chaining, Parallel Priority, Priority Encoder, Mask Register, and Vector Address.
  • Explain how Daisy Chaining serial lines propagate the acknowledge signal ($PO$) based on peripheral device priority order.
  • Construct the truth table for a 4-input Priority Encoder circuit mapping active requests to priority indexes.
  • Contrast Daisy Chaining and Parallel Priority schemes in terms of speed, pin requirements, and cost.
  • Evaluate the flexibility of software-configurable Mask Registers in dynamically modifying interrupt priorities.
Prerequisites

Before studying this chapter, you should review Chapter 3.8: Modes of Transfer to understand interrupts and context switches.

1. Coordinated Interrupt Arbitration

When multiple peripherals (disk drives, printers, keyboards) are connected to a CPU, they can request service simultaneously. Software polling to resolve conflicts introduces execution delays. Hardware **Priority Interrupt** units resolve requests instantly within a clock cycle.

2. Daisy Chaining Priority Interrupt

**Daisy Chaining** is a serial priority scheme. Devices are connected in series based on priority.

  • The Interrupt Acknowledge ($INTACK$) signal from the CPU is wired to the **Priority In ($PI$)** line of the first device.
  • If device 1 is requesting service, it intercepts the signal and places its **Vector Address** on the data bus. If it is not requesting service, it propagates the signal to its **Priority Out ($PO$)** line, which connects to the $PI$ line of the next device.
  • **Bottleneck**: Propagation delay is proportional to the number of serial devices ($O(N)$), slowing high-priority response speeds.

3. Parallel Priority Interrupt Hardware

**Parallel Priority** uses registers and combinational logic to evaluate requests in parallel ($O(1)$ time):

  1. **Interrupt Register ($I$)**: Flags active hardware lines (inputs $I_0-I_3$).
  2. **Mask Register ($M$)**: Configures which lines are enabled. Software writes to $M$ to temporarily disable specific devices.
  3. **Priority Encoder**: Logic circuit that outputs the binary index of the highest priority active, unmasked interrupt.
  4. **Vector Address Generator**: Translates the encoder index into the memory address of the target ISR.

4. Deriving the Priority Encoder Logic

Consider a 4-input priority encoder where input priority order is $I_3 > I_2 > I_1 > I_0$. We map requests to outputs $x, y$, and status flag $INT$:

I3 I2 I1 I0 x y INT
0 0 0 0 d d 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1

Deriving the Boolean equations yields: $$x = I_3 + I_2 \bar{I}_3$$ $$y = I_3 + \bar{I}_2 I_1 \bar{I}_3$$ $$INT = I_3 + I_2 + I_1 + I_0$$

5. Worked Examples & Traces

Execution Trace

Worked Example 3.9.1: Parallel Priority Mask Resolution

**Problem**: Trace how the priority encoder outputs are resolved when: - Interrupt Register states: $I_0 = 1$ (Keyboard), $I_1 = 1$ (Printer), $I_2 = 1$ (Disk Drive), $I_3 = 0$. - Mask Register states: $M_0 = 1$ (enabled), $M_1 = 1$ (enabled), $M_2 = 0$ (masked/disabled). - Priority Order: $I_3 > I_2 > I_1 > I_0$.

**Step-by-Step Resolution Trace**:

  1. **Apply Mask bits**: The active enabled requests ($R_j = I_j \wedge M_j$) are computed: - $R_0 = 1 \wedge 1 = 1$ (Keyboard requesting) - $R_1 = 1 \wedge 1 = 1$ (Printer requesting) - $R_2 = 1 \wedge 0 = 0$ (Disk request masked out) - $R_3 = 0 \wedge 1 = 0$
  2. **Inputs to Priority Encoder**: The priority encoder receives the unmasked requests: $$R_3 R_2 R_1 R_0 = 0011_2$$
  3. **Resolve Highest Priority**: - $R_3 = 0$ - $R_2 = 0$ - $R_1 = 1 \Rightarrow$ This is the highest active unmasked request.
  4. **Compute Output Coordinates**: Map inputs $0011_2$ to priority equations: $$x = R_3 + R_2 \bar{R}_3 = 0 + 0 = 0$$ $$y = R_3 + \bar{R}_2 R_1 \bar{R}_3 = 0 + 1 \times 1 \times 1 = 1$$ $$INT = 0 + 0 + 1 + 1 = 1$$ - Output: $x y = 01_2$, representing device index 1 (Printer).
  5. **Address Branching**: The index $01_2$ is sent to the Vector Address Generator, loading the Printer's ISR.
Viva Voce Q&A

Oral Exam Preparation

**Question**: "What is the primary advantage of Parallel Priority logic over Daisy Chaining?"

**Answer**: Parallel Priority logic resolves requests in constant $O(1)$ gate time, regardless of the number of devices. Daisy Chaining has serial $O(N)$ propagation latency, which slows down service times as devices are added.

Common Mistakes to Avoid

Revision Summary & Takeaways

  • Daisy chaining resolves priority serially using $PI$ and $PO$ lines.
  • Parallel Priority logic uses an Interrupt Register, Mask Register, and Priority Encoder.
  • The priority encoder output routes to a Vector Address Generator to retrieve the ISR address.
How this chapter connects to the next

We have seen how priority logic manages multiple asynchronous CPU interrupts. In Chapter 3.10: Direct Memory Access, we eliminate CPU interrupt routines entirely for high-speed devices, exploring how a DMA controller takes bus control to write blocks directly to RAM.

Check Your Understanding

1. In a parallel priority unit, which register is modified by software to enable or disable specific device interrupts?

References

  1. **ref-notes-syed-arsalaan**: Handwritten Lecture Notes, Page 102 (Priority Encoder Truth Tables). [Local Verified]
  2. **ref-notes-class**: Class COA Lecture Notes, Page 51 (Daisy Chain Timing). [Local Verified]
  3. **ref-book-mano**: M. Morris Mano, *Computer System Architecture*, 3rd Edition, Chapter 11. [Pending Verification]
  4. **ref-lecture-sengupta-34**: Prof. Indranil Sengupta, NPTEL COA, Lecture 34 (Priority Interrupts). [Pending Verification]