3.11 Input-Output Processor

While a DMA controller is configured by the CPU using hardwired registers, the Input-Output Processor (IOP) is an independent co-processor featuring its own instruction set. The IOP runs channel programs directly from memory. This chapter explores IOP channel organizations and CPU-IOP message handshakes.

Learning Objectives

Define terminology: IOP, Channel, Selector Channel, Multiplexer Channel, Channel Command Word (CCW), and CPU-IOP Handshake.
Explain how the IOP runs independent instruction sets (channel programs) directly from main memory.
Construct the logical execution sequence of a CPU-IOP transaction from initialization to interrupt signal completion.
Contrast Selector Channels and Multiplexer Channels in terms of bandwidth and sub-channel interleaving.
Evaluate the efficiency gain of delegating complex I/O interrupt logic to an independent IOP processor.

Prerequisites

Before studying this chapter, you should review Chapter 3.10: Direct Memory Access to understand bus arbitrations and DMA registers.

1. Concept of an Input-Output Processor (IOP)

In systems with massive I/O demands (mainframe systems, high-volume servers), a simple DMA controller is insufficient. Computer designers deploy an **Input-Output Processor (IOP)**. The IOP is a dedicated co-processor that executes its own instructions, called **Channel Commands**, stored in shared **Memory**.

2. Channel Architectures

IOP channels are classified based on device scheduling:

**Selector Channel**: Connects to high-speed devices. It locks the connection to a single device, completing its entire block transfer before releasing the channel.
**Multiplexer Channel**: Connects to multiple slow-speed devices. It interleaves bytes or words from different devices dynamically (Time-Division Multiplexing), allowing concurrent device operations.

3. CPU-IOP Communication Pipeline

Because the CPU and IOP share main memory, they communicate using status variables and command handshakes: - **Start I/O ($SIO$)**: CPU instruction that starts the IOP. - **Channel Command Word ($CCW$)**: IOP instruction specifying the operation, data address, and count. - **Channel Status Word ($CSW$)**: Status word written to memory by the IOP upon completion.

4. Worked Examples & Traces

Execution Trace

Worked Example 3.11.1: SIO Handshake Sequence

**Problem**: Trace the CPU-IOP communication protocol when executing a block write operation to disk.

**Step-by-Step Transaction Trace**:

**Compile Channel Program**: The CPU writes a series of Channel Command Words ($CCW$) into main memory, outlining the disk write commands, RAM buffer offsets, and block sizes.
**Send Command**: The CPU places the starting address of the channel program in memory, then executes the **Start I/O ($SIO$)** instruction.
**Acknowledge**: The IOP intercepts $SIO$, accesses memory, reads the first $CCW$, and returns a status code to the CPU indicating the channel has started.
**Parallel Execution**: - **CPU**: Continues normal program execution. - **IOP**: driving the local **Address Bus** and **Control Bus**, transfers data from memory to disk.
**Interrupt Check**: Once the word count reaches 0, the IOP writes a **Channel Status Word ($CSW$)** to memory, then asserts the CPU interrupt line.
**Complete**: The CPU branches to the I/O interrupt routine, reads the $CSW$ from memory, confirms the transfer was successful, and clears the interrupt.

Viva Voce Q&A

Oral Exam Preparation

**Question**: "How does an IOP differ from a standard DMA controller?"

**Answer**: A standard DMA controller is configured by CPU register writes for every block. An IOP is an independent CPU-like co-processor that executes its own channel program instructions ($CCW$) directly from memory, allowing it to manage complex transfers and multiple devices without CPU intervention.

Common Mistakes to Avoid

Warning: Common Student Pitfalls

**Confusing instruction origin**: Assuming the CPU executes the channel command words ($CCW$) directly. The IOP reads and executes $CCW$ commands independently.
**Selector vs. Multiplexer bandwidth**: Overlooking that selector channels are used for high-speed devices because multiplexing low-speed cycles on high-speed lines would create bottlenecks.

Revision Summary & Takeaways

IOP is an independent co-processor that runs Channel Programs stored in RAM.
Selector channels dedicate bandwidth to one device; Multiplexer channels interleave low-speed devices.
Communication uses $SIO$ instructions, $CCW$ programs, and $CSW$ interrupts.

How this chapter connects to the next

We have completed Unit III, examining how memory and I/O architectures interface with the processor. In Chapter 4.1: RISC vs. CISC, we begin Unit IV, analyzing instruction set architectures (ISA) and comparing RISC and CISC design paradigms.

Check Your Understanding

1. What is the instruction block executed by an IOP called?

References

**ref-notes-syed-arsalaan**: Handwritten Lecture Notes, Page 110 (IOP Flowcharts). [Local Verified]
**ref-notes-class**: Class COA Lecture Notes, Page 52 (Selector Channels). [Local Verified]
**ref-book-mano**: M. Morris Mano, *Computer System Architecture*, 3rd Edition, Chapter 11. [Pending Verification]
**ref-lecture-sengupta-36**: Prof. Indranil Sengupta, NPTEL COA, Lecture 36 (IOP). [Pending Verification]