4.1 RISC vs CISC Architectures
An analysis of the two dominant instruction set architecture philosophies — Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC) — their design principles, trade-offs, and convergence in modern processors.
Learning Objectives
- Explain the fundamental design philosophies behind RISC and CISC architectures.
- Compare RISC and CISC processors across at least 8 architectural parameters.
- Describe the register window mechanism and its role in reducing memory accesses.
- Evaluate the trade-offs between RISC and CISC designs for a given workload.
- Trace the historical evolution from pure RISC/CISC to modern hybrid architectures.
- Analyze how modern x86 CISC processors internally translate instructions into RISC-like micro-operations.
Prerequisites
Before studying this chapter, ensure you have reviewed the following topics:
- Chapter 1.7: Instruction Formats & Addressing Modes (understanding instruction lengths and register access)
- Chapter 2.3: Hardwired Control Unit (the execution speedups of hardwired control pathways)
- Chapter 2.4: Control Memory & Address Sequencing (understanding microprogrammed sequencing overhead)
1. Introduction to ISA Design Philosophy
The Instruction Set Architecture (ISA) serves as the primary boundary between hardware and software. How an ISA is designed heavily dictates compiler complexity, instruction execution logic, and microarchitecture implementation. Historically, ISA design has evolved along a spectrum defined by two primary philosophies: Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC).
To evaluate these philosophies, we refer to the fundamental **CPU Performance Equation**:
Equation 4.1.1: The CPU Performance Equation, where IC = Instruction Count, CPI = Cycles Per Instruction, and T_clk = Clock Cycle Time.
CISC architectures attempt to minimize the **Instruction Count (IC)** by providing highly complex instructions that perform multiple sub-operations (e.g., loading data, adding, and storing back to memory in one instruction). This reduction in IC comes at the cost of an increased **Cycles Per Instruction (CPI)** and more complex microprogramming hardware.
Conversely, RISC architectures prioritize minimizing **CPI** (aiming for exactly 1.0 cycle per instruction) by utilizing simple, uniform, and fixed-length instructions. This design allows for efficient instruction pipelining, shifting the burden of instruction optimization onto the compiler, which increases the overall **Instruction Count (IC)**.
Exam Tip: Performance Balance
Always remember: $$\text{CPI}_{\text{RISC}} < \text{CPI}_{\text{CISC}}$$ but $$\text{IC}_{\text{RISC}} > \text{IC}_{\text{CISC}}$$. A faster clock frequency ($1/T_{\text{clk}}$) in RISC often offsets the larger instruction count, resulting in lower total execution time.
2. CISC Architecture — Design Principles
Complex Instruction Set Computing (CISC) emerged during the mainframe era (1960s–1980s) when memory was extremely expensive and slow. To maximize code density and minimize memory usage, designers sought to close the "semantic gap"—the conceptual distance between high-level languages (like Fortran or C) and machine instructions.
Key CISC Characteristics:
- Variable-Length Instruction Formats: Instructions range from 1 byte to 15+ bytes (e.g., Intel x86), matching the parameters required by specific addressing modes.
- Complex Addressing Modes: Supports indirect memory addressing and indexed references within a single instruction (e.g., base-plus-index-times-scale).
- Memory-to-Memory Operations: Instructions can directly read operands from memory, execute arithmetic, and write results back to memory.
- Microprogrammed Control Units: Because instructions are highly variable and complex, executing them requires a microprogram lookup inside a control ROM, leading to high CPI values.
Typical CISC examples include the IBM System/360, VAX-11, and the classic Intel x86 family.
3. RISC Architecture — Design Principles
By the late 1970s, research by John Cocke (IBM), David Patterson (Berkeley), and John Hennessy (Stanford) revealed that compilers rarely generated complex CISC instructions, as simple loads, stores, and arithmetic operations comprised over 80% of actual workloads.
Key RISC Characteristics:
- Fixed-Length Instruction Formats: Every instruction is exactly 32 bits (or 16 bits in compressed subsets), which simplifies fetch-decode pipelines.
- Load/Store Architecture: Only specific `Load` and `Store` instructions access memory. Arithmetic and logical operations can only execute on registers.
- Hardwired Control Units: Minimizes decode pathways to allow single-cycle execution of instructions.
- Large Register File: Provides ample high-speed registers to store temporary variables, minimizing memory read/write cycles.
- Simple Addressing Modes: Supports only basic addressing configurations (typically register-indirect or register-plus-offset).
Typical RISC architectures include MIPS, ARM, SPARC, PowerPC, and the open RISC-V ISA.
Common Pitfall: Terminology Confusion
Do not confuse "RISC = fewer instructions" with "RISC = simpler instructions". Modern RISC-V or ARM processors may have hundreds of instructions, but each instruction remains simple, executes in uniform cycles, and accesses memory only via explicit load/store operations.
4. Overlapping Register Windows in RISC Processors
Because RISC architectures perform operations entirely on registers, procedure calls (which involve passing parameters and saving return states) can quickly saturate the register file, causing memory "spill" overhead.
To address this bottleneck, Berkeley RISC introduced the Overlapping Register Window mechanism. Instead of saving and restoring registers to memory during procedure calls, the hardware provides a large physical register file divided into overlapping windows. When procedure A calls procedure B, the active register window shifts, making procedure A's *Output* registers procedure B's *Input* registers.
Equation 4.1.2: Total physical registers required (W) where G = Globals, N = Number of windows, L = Locals, and O = Overlap registers.
The register file is organized as a circular buffer. A single procedure window consists of:
- Input Registers (In): Registers holding incoming parameters from the caller.
- Local Registers (Local): Registers allocated for the local variables of the active procedure.
- Output Registers (Out): Registers holding parameters to pass to the next callee procedure.
- Global Registers (Global): A set of registers visible to all procedures at all times.
Hardware Spills & Window Overflows
When procedure nested calls exceed the physical number of windows ($N$), a **Window Overflow** exception occurs. The operating system must catch this trap and write the oldest procedure registers to memory (the stack), freeing up a window.
5. RISC vs CISC — Comprehensive Comparison
To summarize the detailed design differences, the table below highlights the architectural parameters of each philosophy:
| Architectural Parameter | RISC (Reduced) | CISC (Complex) |
|---|---|---|
| Instruction Set Size | Small (under 150 base instructions) | Large (300 to 1000+ instructions) |
| Instruction Length | Fixed (typically 32-bit) | Variable (1 to 15+ bytes) |
| Memory Access | Load/Store instructions only | Direct memory operations allowed |
| Addressing Modes | Few, simple modes | Many, complex modes |
| Control Unit Design | Hardwired (speed-optimized) | Microprogrammed (ROM-based) |
| Cycles Per Instruction (CPI) | Close to 1.0 (single-cycle ideal) | High (2.0 to 10.0+ cycles) |
| Register Count | Large (32 to 128+ registers) | Small (typically 8 to 16 registers) |
| Code Density | Low (larger binary files) | High (compact binary files) |
6. The Convergence — Modern Hybrid Architectures
Today, the strict boundary between RISC and CISC has collapsed. Modern desktop and server processors are almost entirely **hybrid architectures**.
For instance, the **Intel Core i9** (technically a CISC architecture) features a complex front-end that decodes variable-length x86 instructions into simple, fixed-length RISC-like **micro-operations ($\mu\text{-ops}$)**. These $\mu\text{-ops}$ are then executed on a high-speed out-of-order RISC back-end. Conversely, modern **ARM** processors (traditionally RISC) have incorporated complex floating-point instruction extensions and vector operations (NEON, SVE) to handle AI and database workloads, closing the semantic gap.
7. Worked Examples
RISC vs CISC CPU Time Comparison
Problem: An algorithm is compiled into machine code for both a RISC and a CISC processor. The resulting program parameters are as follows:
- **RISC Program**: Instruction Count ($IC$) = 150,000, Average $CPI$ = 1.25, Clock Frequency ($f_{\text{clk}}$) = 3.0 GHz.
- **CISC Program**: Instruction Count ($IC$) = 50,000, Average $CPI$ = 4.5, Clock Frequency ($f_{\text{clk}}$) = 2.5 GHz.
Calculate the total CPU execution time for both systems and determine which processor executes the program faster.
Solution:
Using Equation 4.1.1: $$\text{CPU Time} = \frac{IC \times CPI}{f_{\text{clk}}}$$
- For the RISC Processor: $$\text{CPU Time}_{\text{RISC}} = \frac{150,000 \times 1.25}{3.0 \times 10^9 \text{ Hz}} = \frac{187,500}{3.0 \times 10^9} = 6.25 \times 10^{-5} \text{ seconds (or 62.5 }\mu\text{s)}$$
- For the CISC Processor: $$\text{CPU Time}_{\text{CISC}} = \frac{50,000 \times 4.5}{2.5 \times 10^9 \text{ Hz}} = \frac{225,000}{2.5 \times 10^9} = 9.0 \times 10^{-5} \text{ seconds (or 90.0 }\mu\text{s)}$$
Conclusion: The RISC processor executes the program faster than the CISC processor, taking **62.5 $\mu\text{s}$** compared to **90.0 $\mu\text{s}$**, because its lower CPI and higher clock frequency more than compensate for its higher instruction count.
Register Window Calculations
Problem: A RISC processor implements overlapping register windows with the following specifications: global registers $G = 8$, local registers $L = 10$, and overlapping registers $O = 6$. The CPU features $N = 8$ overlapping windows. Calculate:
- The total physical register count in the register file ($W$).
- The number of registers visible to any active procedure at any given time.
Solution:
- Total Physical Register Count ($W$): Using Equation 4.1.2: $$W = G + N \times (L + O)$$ Substitute the given variables: $$W = 8 + 8 \times (10 + 6) = 8 + 8 \times 16 = 8 + 128 = 136 \text{ physical registers}$$
- Registers Visible to an Active Procedure: Each active procedure sees: $$\text{Visible Registers} = \text{Input Registers} + \text{Local Registers} + \text{Output Registers} + \text{Global Registers}$$ Because overlapping registers act as both Inputs and Outputs: $$\text{Visible Registers} = O + L + O + G = 2 \times O + L + G$$ $$\text{Visible Registers} = 2 \times 6 + 10 + 8 = 12 + 10 + 8 = 30 \text{ registers}$$
Conclusion: The register file contains a total of **136 physical registers**, with **30 registers** logically visible to any active procedure.
Assembly Tracing: RISC vs CISC Instructions
Problem: Design and analyze code sequences to perform a vector addition element-wise operation $$C[i] = A[i] + B[i]$$ using (a) CISC instruction formats with memory direct addressing, and (b) RISC load-store instruction formats. Compute total instruction counts and comparative memory access footprints.
Solution:
-
CISC Implementation:
A CISC processor can execute this in one memory-to-memory instruction:
ADD C[Ri], A[Ri], B[Ri] ; Memory direct operands added
* **Instruction Count**: 1 * **Memory Accesses**: 4 (1 to fetch instruction, 2 to read operands A and B, 1 to store result C) -
RISC Implementation:
A load/store RISC architecture must decouple memory access from operation execution:
LD R1, A[R2] ; Load Operand A into Register R1 LD R3, B[R2] ; Load Operand B into Register R3 ADD R4, R1, R3 ; ALU executes add on registers ST R4, C[R2] ; Store Register R4 back to memory C
* **Instruction Count**: 4 * **Memory Accesses**: 7 (4 to fetch instructions, 2 to load operands A and B, 1 to store result C)
Conclusion: While the CISC instruction is highly compact, its complex datapath requires a microprogrammed loop taking multiple cycles. The 4 RISC instructions, although taking more memory space, can be executed in a hardwired 5-stage pipeline near a CPI of 1.
8. Practice Numerical Problems
Problem 4.1.1: A program is executed on two processors:
- **Processor X (CISC)**: Runs at 600 MHz, taking 4 complex instructions with a CPI of 5.5.
- **Processor Y (RISC)**: Runs at 900 MHz, taking 10 simple instructions with a CPI of 1.1.
Calculate which processor executes the program faster and compute the percentage speedup.
Answer: Processor Y (RISC) takes 12.2 $\mu\text{s}$, while Processor X takes 36.7 $\mu\text{s}$. Speedup of Y over X is **2.00× (200% speedup)**.
Problem 4.1.2: A SPARC-based RISC CPU has 10 global registers and 8 procedure windows. Each window contains 8 local registers and has an overlap of 6 registers with adjacent windows. Calculate the total number of physical registers inside this CPU.
Answer: $$W = 10 + 8 \times (8 + 6) = 10 + 8 \times 14 = 122 \text{ registers}$$.
Problem 4.1.3: A compiler optimization reduces the Instruction Count of a RISC program by 20%, but increases the average CPI by 10% due to data dependencies. Assuming the clock cycle time remains constant, calculate the net performance speedup.
Answer: $$\text{New Time} = 0.8 \times IC \times 1.1 \times CPI \times T = 0.88 \times \text{Old Time}$$. Speedup is $$\frac{1}{0.88} - 1 = 13.6\%$$.
9. Assessment Bank (GATE & University)
GATE Questions
GATE Q4.1.1: Which of the following is/are characteristic(s) of a RISC processor?
- All instructions are executed in a single clock cycle under ideal conditions.
- Direct memory addressing is supported for arithmetic operands.
- Features a microprogrammed control unit ROM to decode variable instructions.
- Possesses overlapping register windows to accelerate procedure calls.
(A) I and II only (B) II and III only (C) I and IV only (D) I, II and IV only
Answer & Analysis: **(C)**. I is correct (ideal RISC pipelining strives for CPI=1). II is incorrect (RISC is a load/store architecture; memory operands cannot be directly manipulated by ALU). III is incorrect (RISC uses hardwired control). IV is correct (overlapping register windows are a classic Berkeley RISC/SPARC feature).
GATE Q4.1.2: In a RISC processor with overlapping register windows, there are 8 global registers, and each procedure window contains 16 registers. The overlap between caller and callee is 4 registers. How many local registers are available to each procedure window?
(A) 4 (B) 8 (C) 12 (D) 16
Answer & Analysis: **(B)**. In each window, the 16 registers are split into Input (overlap), Local, and Output (overlap). Since caller-callee overlap is 4, both Input and Output sizes are 4. Thus: $$\text{Local} = 16 - (\text{In} + \text{Out}) = 16 - (4 + 4) = 8 \text{ local registers}$$. Therefore, the correct option is (B).
University Exam Questions
UQ 4.1.1: Compare RISC and CISC architectures across at least 8 key parameters. Which architecture is commonly utilized in mobile embedded devices, and why? (8 marks)
UQ 4.1.2: Discuss the overlapping register window architecture implemented in RISC processors. How does this mechanism accelerate procedure execution compared to stack memory operations? (5 marks)
UQ 4.1.3: How do modern Intel x86 processors bridge the design gap between RISC and CISC? Detail the decode pipeline and micro-op execution. (10 marks)
Viva Voce Questions
VQ 4.1.1: What is the "semantic gap" in Computer Organization, and why did CISC architectures try to close it?
Model Answer: The semantic gap is the conceptual difference between high-level programming syntax (like loops, structs, operations) and machine-level binary code. CISC designers tried to close this gap by creating complex instructions that matched high-level compiler expressions, hoping to make writing compilers easier and saving memory code space.
VQ 4.1.2: What happens when register windows overflow in a RISC architecture?
Model Answer: A register window overflow occurs when nested procedure calls exceed the physical count of register windows in the CPU. When this happens, a hardware trap is generated, prompting the operating system to save the register contents of the oldest procedure window onto the memory stack, freeing that window for the new procedure.
🎯 Key Takeaways
- RISC simplifies instruction design to target CPI = 1.0, leveraging hardwired control and load/store structures.
- CISC aims to reduce instruction counts by using complex, variable-length instructions and microprogrammed ROMs.
- Register Windows optimize procedure call overhead in RISC by sharing overlapping input/output registers between caller and callee.
- Modern Hybrid CPUs merge the two, using a CISC decoder front-end to break instructions into RISC-like micro-ops.