Glossary of Key Concepts

An authoritative directory of foundational terms and abbreviations in Computer Organization and Architecture.

1. Alphabetical Term Directory

ALU (Arithmetic Logic Unit)

The combinational digital circuit within a processor responsible for executing all arithmetic operations (addition, subtraction, multiplication) and logical operations (AND, OR, XOR, shifts).

First Occurrence: Chapter 1.1 Chapter Links: Ch 1.1 Overview, Ch 2.1 ALU Design Related Terms: Accumulator, Register File, CU

MAR (Memory Address Register)

A dedicated CPU register that holds the physical memory address currently being read from or written to by the processor.

First Occurrence: Chapter 1.3 Chapter Links: Ch 1.3 Registers, Ch 1.6 Instruction Cycle Related Terms: MDR, Memory Bus

MDR (Memory Data Register)

Also known as the Memory Buffer Register (MBR). A CPU register that holds the data read from memory or the data to be written to memory.

First Occurrence: Chapter 1.3 Chapter Links: Ch 1.3 Registers, Ch 1.6 Instruction Cycle Related Terms: MAR, Memory Bus

PC (Program Counter)

A critical control register containing the address of the next instruction to be fetched and executed.

First Occurrence: Chapter 1.3 Chapter Links: Ch 1.3 Registers, Ch 1.6 Instruction Cycle Related Terms: Instruction Register, Branching

IR (Instruction Register)

A control register that stores the binary instruction currently being decoded and executed by the CPU.

First Occurrence: Chapter 1.3 Chapter Links: Ch 1.3 Registers, Ch 1.6 Instruction Cycle Related Terms: PC, Decoder

Cache Memory

A small, high-speed SRAM block placed between the CPU and main DRAM memory to store frequently accessed data, reducing average latency.

First Occurrence: Chapter 3.3 Chapter Links: Ch 3.3 Mapping, Ch 3.4 Writing Policies Related Terms: SRAM, Direct Mapping, Cache Coherence

DMA (Direct Memory Access)

An input-output transfer technique where an external controller transfers data blocks directly to and from main memory without involving the CPU, minimizing interrupt overhead.

First Occurrence: Chapter 3.10 Chapter Links: Ch 3.10 DMA Related Terms: IOP, Bus Master

Pipelining

An implementation method that overlaps the execution of multiple instructions by dividing the processor execution pathway into cascading stages.

First Occurrence: Chapter 4.2 Chapter Links: Ch 4.2 Pipelining Related Terms: Data Hazards, Speedup

Flynn's Classification

A taxonomy proposed by Michael Flynn classifying parallel processing systems according to the multiplicity of instruction and data streams (SISD, SIMD, MISD, MIMD).

First Occurrence: Chapter 4.4 Chapter Links: Ch 4.4 Flynn's Classification Related Terms: SIMD, MIMD, Vector Processing

MESI Protocol

A snooping cache coherence protocol tracking block states (Modified, Exclusive, Shared, Invalid) to preserve consistency in shared-memory multiprocessors.

First Occurrence: Chapter 4.3 Chapter Links: Ch 4.3 Parallel Processing Related Terms: Cache Coherence, Snooping

Booth's Multiplication Algorithm

A hardware multiplication algorithm that treats consecutive strings of 1s in the multiplier with a single subtraction and addition, reducing cycle operations.

First Occurrence: Chapter 1.5 Chapter Links: Ch 1.5 Arithmetic Related Terms: Arithmetic Multiplier

IEEE 754 Standard

The dominant technical standard defining formats and rounding policies for floating-point arithmetic (single-precision 32-bit and double-precision 64-bit representations).

First Occurrence: Chapter 1.5 Chapter Links: Ch 1.5 Arithmetic Related Terms: Mantissa, Exponent Bias

2. Textbook-Style Alphabetical Index

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